Alternatives and similar repositories for painless:

Users that are interested in painless are comparing it to the libraries listed below

• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆28Updated 8 months ago
• fangwenji / tacas23-wasim
  ☆12Updated 2 years ago
• gipsyh / rIC3-HWMCC24
  rIC3 model checker for Hardware Model Checking Competition 2024(HWMCC'24) submission
  ☆11Updated 7 months ago
• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆25Updated last year
• muhos / ParaFROST
  A Parallel SAT Solver with GPU Accelerated Inprocessing
  ☆102Updated last week
• CoriolisSP / FuzzBtor2
  Random Generator of Btor2 Files
  ☆10Updated last year
• jetafese / btor2mlir
  Bᴛᴏʀ2MLIR: A Format and Toolchain for Hardware Verification
  ☆13Updated 4 months ago
• arminbiere / aiger
  AIGER And-Inverter-Graph Library
  ☆71Updated last week
• gipsyh / rIC3
  Hardware Formal Verification Tool
  ☆42Updated last week
• shaowei-cai-group / ParKissat-RS
  Parallel SAT solver that won the SAT Competition 2022 by a large margin (24% faster than the 2nd ranked solver)
  ☆24Updated 2 years ago
• Gy-Hu / HWMCC24-benchmark
  Collection for submission (Hardware Model Checking Benchmark)
  ☆9Updated 5 months ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆70Updated 4 years ago
• upscale-project / generic-sqed-demo
  ☆13Updated 4 years ago
• JKomp / AIGER
  Python version of tools to work with AIG formatted files
  ☆10Updated 11 months ago
• d-kfmnn / amulet2
  AMulet 2. - A better AIG Multiplier Examination Tool
  ☆24Updated 2 years ago
• amahzoon / genmul
  ☆16Updated 4 years ago
• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆20Updated 3 months ago
• RafaelTupynamba / SMTSampler
  SMTSampler: Efficient Stimulus Generation from Complex SMT Constraints
  ☆25Updated 5 years ago
• iscas-tis / CHA
  ☆18Updated 9 months ago
• makaimann / ride-core-demo
  A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core
  ☆12Updated 5 years ago
• amahzoon / RevSCA-2.0
  ☆10Updated 5 years ago
• mvcisback / py-aiger
  py-aiger: A python library for manipulating sequential and combinatorial circuits encoded using `and` & `inverter` gates (AIGs).
  ☆43Updated 3 months ago
• arminbiere / gimsatul
  ☆34Updated 9 months ago
• mikeurbach / egg-netlist-synthesizer
  Using e-graphs to synthesize netlists from boolean logic.
  ☆14Updated last year
• hwmcc / btor2tools
  A generic parser and tool package for the BTOR2 format.
  ☆41Updated 4 months ago
• aman-goel / avr
  Reads a state transition system and performs property checking
  ☆78Updated last month
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆42Updated this week
• Gy-Hu / AIG2INV
  DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction (ASP-DAC 2024)
  ☆11Updated last year
• ekiwi / open-source-formal-verification-for-chisel
  ☆11Updated 3 years ago
• gussmith23 / lakeroad
  FPGA synthesis tool powered by program synthesis
  ☆41Updated this week