shaowei-cai-group / EasySATLinks
A Simple CDCL Solver
☆33Updated 2 years ago
Alternatives and similar repositories for EasySAT
Users that are interested in EasySAT are comparing it to the libraries listed below
Sorting:
- Parallel SAT solver that won the SAT Competition 2022 by a large margin (24% faster than the 2nd ranked solver)☆25Updated 2 years ago
- An advanced circuit-based sat solver☆35Updated 8 months ago
- A high-efficiency hybrid solving CEC algorithm☆14Updated 2 years ago
- SATZilla SAT feature extraction tool☆11Updated last year
- Bit-bLAsting solving Non-linear integer constraints.☆22Updated 3 months ago
- PyTorch implementation of NeuroSAT☆28Updated 2 years ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆36Updated last year
- ☆19Updated 8 months ago
- Random Generator of Btor2 Files☆10Updated 2 years ago
- NLocalSAT; Boosting Local Search with Solution Prediction☆18Updated 2 years ago
- A generic parser and tool package for the BTOR2 format.☆43Updated last month
- AMulet 2. - A better AIG Multiplier Examination Tool☆26Updated 3 years ago
- DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction (ASP-DAC 2024)☆11Updated last year
- AIGER And-Inverter-Graph Library☆88Updated 2 months ago
- Logic Synthesis System from UC Berkeley (Unofficial Distribution)☆15Updated 6 years ago
- Recent papers related to hardware formal verification.☆73Updated 2 years ago
- This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".☆24Updated 2 years ago
- ☆18Updated 4 years ago
- Reads a state transition system and performs property checking☆88Updated last month
- SMTSampler: Efficient Stimulus Generation from Complex SMT Constraints☆29Updated 6 years ago
- Hardware Formal Verification Tool☆69Updated this week
- ☆15Updated 2 years ago
- py-aiger: A python library for manipulating sequential and combinatorial circuits encoded using `and` & `inverter` gates (AIGs).☆48Updated 10 months ago
- LLM Evaluation Benchmark on Hardware Formal Verification☆30Updated 6 months ago
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆22Updated 6 months ago
- ☆33Updated 3 years ago
- ☆15Updated 2 years ago
- C++ implementation of FRAIGs. Won the 1st place in 2018 Cadence-sponsored contest in NTU DSnP.☆10Updated 5 years ago
- A framework to ease parallelization of sequential SAT solvers☆26Updated 5 months ago
- ☆12Updated 2 years ago