Alternatives and similar repositories for EasySAT

Users that are interested in EasySAT are comparing it to the libraries listed below

• shaowei-cai-group / X-SAT
  An advanced circuit-based sat solver
  ☆29Updated 6 months ago
• HybridCEC / Hybrid-CEC
  A high-efficiency hybrid solving CEC algorithm
  ☆13Updated 2 years ago
• ryanzhangfan / NeuroSAT
  PyTorch implementation of NeuroSAT
  ☆28Updated 2 years ago
• shaowei-cai-group / ParKissat-RS
  Parallel SAT solver that won the SAT Competition 2022 by a large margin (24% faster than the 2nd ranked solver)
  ☆24Updated 2 years ago
• hadarshavit / revisiting_satzilla
  SATZilla SAT feature extraction tool
  ☆10Updated last year
• fuqi-jia / BLAN
  Bit-bLAsting solving Non-linear integer constraints.
  ☆22Updated last month
• myxxxsquared / NLocalSAT
  NLocalSAT; Boosting Local Search with Solution Prediction
  ☆18Updated 2 years ago
• hwmcc / btor2tools
  A generic parser and tool package for the BTOR2 format.
  ☆41Updated 3 months ago
• d-kfmnn / amulet2
  AMulet 2. - A better AIG Multiplier Examination Tool
  ☆25Updated 2 years ago
• Yu-Maryland / MapTune
  MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…
  ☆21Updated 4 months ago
• hkustgz-zhang-lab / ABCPaperCheck
  Research paper based on or related to ABC.
  ☆51Updated last month
• cure-lab / DeepGate
  This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".
  ☆23Updated 2 years ago
• Gy-Hu / AIG2INV
  DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction (ASP-DAC 2024)
  ☆11Updated last year
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆35Updated last year
• arminbiere / aiger
  AIGER And-Inverter-Graph Library
  ☆86Updated 3 weeks ago
• shaowei-cai-group / z3pp
  ☆48Updated last year
• CoriolisSP / FuzzBtor2
  Random Generator of Btor2 Files
  ☆10Updated last year
• aman-goel / avr
  Reads a state transition system and performs property checking
  ☆85Updated 5 months ago
• achieve-lab / assertion_data_for_LLM
  ☆16Updated 6 months ago
• gipsyh / rIC3
  Hardware Formal Verification Tool
  ☆62Updated last week
• cure-lab / DeepGate2
  ☆15Updated 2 years ago
• ByronHsu / FRAIGs
  C++ implementation of FRAIGs. Won the 1st place in 2018 Cadence-sponsored contest in NTU DSnP.
  ☆10Updated 4 years ago
• hkustgz-zhang-lab / HW-Formal-Paper
  Recent papers related to hardware formal verification.
  ☆72Updated last year
• zshi0616 / DeepGate2
  ☆28Updated last year
• OSCC-Project / iMap
  Logic optimization and technology mapping tool.
  ☆19Updated last year
• RafaelTupynamba / SMTSampler
  SMTSampler: Efficient Stimulus Generation from Complex SMT Constraints
  ☆29Updated 5 years ago
• amahzoon / genmul
  ☆17Updated 4 years ago
• lijwen2748 / simplecar
  ☆15Updated 2 years ago
• zhaoyu-li / G4SATBench
  [TMLR 2024] G4SATBench: Benchmarking and Advancing SAT Solving with Graph Neural Networks
  ☆35Updated last year
• saleh1204 / sis
  Logic Synthesis System from UC Berkeley (Unofficial Distribution)
  ☆15Updated 6 years ago