This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.
☆15Jun 26, 2024Updated 2 years ago
Alternatives and similar repositories for Matrix-Multiplication-Using-Systolic-Arrays-Chip-Design-and-Verification
Users that are interested in Matrix-Multiplication-Using-Systolic-Arrays-Chip-Design-and-Verification are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A 4x4 Weight Stationary Systolic Array Implementation☆15Oct 16, 2023Updated 2 years ago
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆12Jan 8, 2022Updated 4 years ago
- 24bit CPU with integrated GPU made in Logisim☆15Mar 3, 2026Updated 4 months ago
- A hardware accelerator for General Matrix Multiply, developed in SystemC using ESP.☆20May 26, 2021Updated 5 years ago
- ☆13Nov 13, 2022Updated 3 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- 2D Systolic Array Multiplier☆35Updated this week
- ☆12Jun 18, 2020Updated 6 years ago
- Implementation of PSO Algorithm to Optimize SVM☆11May 18, 2019Updated 7 years ago
- Learning Machine Learning with TensorFlow☆10Feb 20, 2017Updated 9 years ago
- ☆17Jul 10, 2026Updated last week
- ☆17Apr 7, 2022Updated 4 years ago
- ☆10Nov 4, 2022Updated 3 years ago
- My Solutions to Nomura's GM Quant Challenge 2022☆15Jun 28, 2022Updated 4 years ago
- ☆15Aug 10, 2023Updated 2 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- eXP-RAN - an Emulator for Gaining Experience with Radio Access Networks, Edge Computing, and Slicing☆18Nov 14, 2022Updated 3 years ago
- ☆14Oct 8, 2024Updated last year
- NoC simulation using gem5 (a simple tul)☆16Mar 23, 2024Updated 2 years ago
- LLM-aided Hardware Design and Verification☆34May 11, 2026Updated 2 months ago
- ☆13Jan 9, 2023Updated 3 years ago
- A convolutional autoencoder for feature extraction, with an SVM for image classification.☆10Jan 30, 2019Updated 7 years ago
- ☆19Apr 7, 2026Updated 3 months ago
- Strategy-oriented Option Trading and Research Platform☆18Updated this week
- 哈尔滨工业大学(深圳)2021年球季学期深度学习体系结构实验☆17Oct 1, 2022Updated 3 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- 卷积神经网络提取特征并用于SVM//www.cnblogs.com/chuxiuhong/p/6132814.html☆16May 10, 2018Updated 8 years ago
- Memory Compiler Tutorial☆14Oct 7, 2020Updated 5 years ago
- A complete UVM TB for verification of single port 64KB RAM☆18Apr 16, 2021Updated 5 years ago
- 使用LDA+SVM进行文本的分类☆22Jul 23, 2017Updated 8 years ago
- Algorithmic C Machine Learning Library☆29Jul 6, 2026Updated 2 weeks ago
- Assignments for Coursera Algorithms: Part 1 & Part 2 and exercises from the https://algs4.cs.princeton.edu textbook.☆24Sep 16, 2023Updated 2 years ago
- Coarse Grained Reconfigurable Arrays with Chisel3☆11Jul 1, 2024Updated 2 years ago
- ☆35Jun 15, 2026Updated last month
- FPGA systolic array AI engine☆37Jan 2, 2026Updated 6 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- 2048 Game created via Verilog, loaded on an FPGA board and VGA monitor.☆12Mar 25, 2022Updated 4 years ago
- ☆16Dec 3, 2022Updated 3 years ago
- FPGA创新设计大赛全国二等奖,Multi-functional Game Console Based on RISC-V.(基于紫光FPGA的RSIC V多功能游戏机)☆11Aug 16, 2024Updated last year
- -Designed and Verified a Bus Functional Model of AHB-LITE Protocol from scratch. -Developed Assertion based verification IP to verify the…☆25Dec 9, 2015Updated 10 years ago
- This is an attempt to fine tune SOTA Large Language Models so as to generate Verilog (VHDL) programmes, detect syntax, logic and human er…☆18Mar 12, 2026Updated 4 months ago
- A FastAPI/Redis/Celery async distributed queues backend with a Redis dashboard☆25Mar 21, 2026Updated 4 months ago
- Large-scale 2D mesh system with dedicated GeMM, on-chip RDMA and Rendez-vous accelerators.☆23Updated this week