purdue-aalp / gpgpu-sim_distribution_oldLinks
GPGPU-Sim provides a detailed simulation model of a contemporary GPU running CUDA and/or OpenCL workloads and now includes an integrated (and validated) energy model, GPUWattch.
☆14Updated 5 years ago
Alternatives and similar repositories for gpgpu-sim_distribution_old
Users that are interested in gpgpu-sim_distribution_old are comparing it to the libraries listed below
Sorting:
- The source code for GPGPUSim+Ramulator simulator. In this version, GPGPUSim uses Ramulator to simulate the DRAM. This simulator is used t…☆57Updated 5 years ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆56Updated 4 years ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆77Updated 6 years ago
- ☆27Updated 2 months ago
- ☆92Updated last year
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago
- Visualization tool for designing mesh Network-on-Chips (NoC) and assisting with architecture research☆13Updated last year
- A novel spatial accelerator for horizontal diffusion weather stencil computation, as described in ICS 2023 paper by Singh et al. (https:/…☆22Updated 2 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆42Updated 8 years ago
- Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 …☆22Updated 4 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆68Updated last year
- Source code of the simulator used in the Mosaic paper from MICRO 2017: "Mosaic: A GPU Memory Manager with Application-Transparent Support…☆49Updated 7 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆18Updated 6 years ago
- A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…☆74Updated 11 months ago
- Heterogeneous simulator for DECADES Project☆32Updated last year
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- cycle accurate Network-on-Chip Simulator☆30Updated 2 years ago
- SST Architectural Simulation Components and Libraries☆98Updated last week
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆22Updated 7 years ago
- ☆65Updated 4 years ago
- ☆75Updated 4 years ago
- agile hardware-software co-design☆50Updated 3 years ago
- SimplePIM is the first high-level programming framework for real-world processing-in-memory (PIM) architectures. Described in the PACT 20…☆27Updated last year
- ☆13Updated 10 years ago
- Artifact for "DX100: A Programmable Data Access Accelerator for Indirection (ISCA 2025)" paper☆13Updated 4 months ago
- ☆33Updated 4 months ago
- ☆25Updated last year
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆41Updated 2 months ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆34Updated last year