PrincetonUniversity / primesim
A parallel and distributed simulator for thousand-core chips
☆22Updated 6 years ago
Related projects ⓘ
Alternatives and complementary repositories for primesim
- The gem5-X open source framework (based on the gem5 simulator)☆38Updated last year
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆22Updated last year
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆36Updated this week
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆39Updated 4 years ago
- This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…☆11Updated 4 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆17Updated 5 years ago
- Manycore platform Simulation tool for NoC-based platform at a Cycle-accurate level☆10Updated 6 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆46Updated 7 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- ordspecsim: The Swarm architecture simulator☆24Updated last year
- upstream: https://github.com/RALC88/gem5☆32Updated last year
- cycle accurate Network-on-Chip Simulator☆25Updated last year
- A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency…☆18Updated 3 years ago
- Tests for example Rocket Custom Coprocessors☆69Updated 4 years ago
- The source code for GPGPUSim+Ramulator simulator. In this version, GPGPUSim uses Ramulator to simulate the DRAM. This simulator is used t…☆49Updated 5 years ago
- Extremely Simple Microbenchmarks☆30Updated 6 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆37Updated 5 years ago
- Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 …☆19Updated 4 years ago
- A High-Level DRAM Timing, Power and Area Exploration Tool☆23Updated 4 years ago
- The RTL source for AnyCore RISC-V☆30Updated 2 years ago
- Hybrid BFS on Xilinx Zynq☆18Updated 9 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆41Updated 7 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆48Updated 4 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆59Updated 11 months ago
- ☆9Updated 2 years ago
- Tutorial Material from the SST Team☆18Updated 6 months ago
- ☆18Updated 3 years ago
- Archives of SystemC from The Ground Up Book Exercises☆28Updated 2 years ago
- ☆15Updated 3 years ago