virtualsecureplatform / V2TT
This is the repository for the transpiler to compile Verilog to C++ code with TFHE library.
☆18Updated 4 years ago
Related projects: ⓘ
- Instruction set simulator for RISC-V☆52Updated 4 years ago
- ☆13Updated 5 years ago
- Constraint geometry processing language☆18Updated 4 years ago
- RISC-V documentation transrate to Japanese.☆72Updated 2 years ago
- Translation of http://chip-architect.com/news/2003_09_21_Detailed_Architecture_of_AMDs_64bit_Core.html☆10Updated 5 years ago
- xv6のテキスト(book-rev6.pdf)を超適当翻訳してPDF化したもの☆28Updated 11 years ago
- nv is a programming language supports non-volatile variable and flexible grammar.☆24Updated 3 years ago
- CR0.CD manipulate Linux Kernel Module as a proc filesystem☆19Updated 5 years ago
- C compiler + hikalium☆33Updated 3 years ago
- RISC-V Simulator written in Rust☆20Updated 4 years ago
- Simple RISC-V emulator☆16Updated 4 years ago
- ☆17Updated this week
- ☆19Updated 4 years ago
- Open source RISC-V IP core for FPGA/ASIC design☆30Updated 2 months ago
- Stacking List Oriented Basic Architecture Allocator☆15Updated 5 years ago
- translation of XV6☆49Updated 6 years ago
- RISC-V (rv32imf) CPU implemented in System Verilog for cpuex2019 @ UTokyo☆13Updated 4 years ago
- Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)☆35Updated 3 years ago
- ☆37Updated 6 years ago
- ☆10Updated this week
- a brief note on extendable and injectable syntax☆19Updated 8 years ago
- RISC-V Software Simulation☆20Updated 5 years ago
- Unofficial website of security camp☆11Updated 2 weeks ago
- A CPU that executes brainf**k language. Can be synthesized on FPGA☆12Updated 7 years ago
- ☆41Updated 6 years ago
- Cyanurus is a Unix-like operating system for ARMv7-A☆47Updated 7 years ago
- 手を動かせばできるLLVMバックエンド チュートリアル（WIP）☆45Updated 2 years ago
- Tiny MIPS for Terasic DE0☆36Updated 10 years ago
- WWWを再構築するぞ！！！☆15Updated 6 years ago
- ☆26Updated last year