Alternatives and similar repositories for Neurram_48core

Users that are interested in Neurram_48core are comparing it to the libraries listed below

• neurosim / 3D_NeuroSim_V1.0
  Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration
  ☆23Updated 3 years ago
• snagiri / CSE237D-PYNQ-SNN-Accelerator
  Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board
  ☆37Updated 6 years ago
• akdimitri / RRAM_COMPILER
  This repository includes the Resistive Random Access Memory (RRAM) Compiler which is designed in the context of the research project of D…
  ☆69Updated 2 years ago
• jeshraghian / snn-accelerator
  ☆26Updated 3 years ago
• neurosim / DNN_NeuroSim_V2.0
  Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)
  ☆52Updated 4 years ago
• SFU-HiAccel / SyncNN
  [FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.
  ☆59Updated 4 years ago
• ChFrenkel / ReckOn
  ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales - HDL source code and documentation.
  ☆85Updated 3 years ago
• zwhexplorer / Spiking-Neural-Network-Accelerator-EE552-project
  Spiking Neural Network Accelerator
  ☆15Updated 3 years ago
• ChFrenkel / tinyODIN
  tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.
  ☆65Updated 2 years ago
• neurosim / DNN_NeuroSim_V1.0
  Benchmark framework of compute-in-memory based accelerators for deep neural network
  ☆43Updated 5 years ago
• neurosim / NeuroSim
  Central repository for all NeuroSim versions. Each version is uploaded in a separate branch. Updates to the versions will be reflected he…
  ☆64Updated 2 months ago
• CRAFT-THU / XB-Sim
  A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration
  ☆34Updated 3 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• awai54st / LUTNet
  ☆58Updated 5 years ago
• neurosim / DNN_NeuroSim_V1.3
  Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)
  ☆72Updated last year
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆57Updated 10 months ago
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆86Updated 3 months ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆46Updated 6 months ago
• fgr1986 / rram_multilevel_driver
  Architecture for RRAM multilevel programming
  ☆17Updated 6 years ago
• AIC2021 / AIC2021_TPU_Template
  Template for project1 TPU
  ☆19Updated 4 years ago
• hyoukjun / OpenSMART
  Public release
  ☆57Updated 5 years ago
• DNN-Accelerators / Open-Source-IPs
  ☆34Updated 6 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆41Updated 3 years ago
• KyleParkJong / Network-on-Chip-Simulator
  Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator
  ☆30Updated last year
• saunak1994 / CyNAPSEv11
  The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL
  ☆34Updated 5 years ago
• MartaAndronic / NeuraLUT
  NeuraLUT-Assemble
  ☆38Updated last week
• Xilinx / logicnets
  Train and deploy LUT-based neural networks on FPGAs
  ☆97Updated last year
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆24Updated 4 years ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆77Updated 2 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆65Updated 6 years ago