EDA claws for analog/digital circuits and device design
☆52Aug 16, 2026Updated last week
Alternatives and similar repositories for EDACraft
Users that are interested in EDACraft are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Contests☆20Jul 28, 2026Updated 3 weeks ago
- 复旦数字集成电路设计自动化项目文档☆11Apr 12, 2025Updated last year
- ☆12Dec 11, 2023Updated 2 years ago
- ☆36Nov 27, 2023Updated 2 years ago
- ☆16Jun 30, 2024Updated 2 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Andes Vector Extension support added to riscv-dv☆19May 29, 2020Updated 6 years ago
- LLM-DSE: Searching Accelerator Parameters with LLM Agents☆17May 22, 2025Updated last year
- A collection of datapath circuit design and verification benchmarks☆19Aug 13, 2026Updated last week
- ☆24May 14, 2025Updated last year
- In this realtime car detection we are using YOLOV8 model also known as Ultralytics, for the detection of vehicles and deep_sort_pytorch. …☆16Feb 8, 2025Updated last year
- Vivado HLS study notes, courses, documents.☆12Dec 7, 2019Updated 6 years ago
- 基于FP16的二维脉动阵列电路设计☆13Feb 23, 2023Updated 3 years ago
- 32位单精度浮点数加法器和除法器是用于执行符合IEEE 754标准的浮点数加法、除法运算的数字电路。这样的电路设计在现代计算机系统中扮演着重要角色,特别是在处理需要高精度计算的任务时。这个小项目实现了一个符合IEEE 754 单精度浮点数标准(32 位)的浮点数加法器与除法…☆15Aug 14, 2025Updated last year
- Logic Synthesis System from UC Berkeley (Unofficial Distribution)☆15Jun 4, 2019Updated 7 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- ☆19Dec 21, 2020Updated 5 years ago
- Compiler Explorer for RTL: synthesize Verilog with Yosys and explore timing paths, logic depth, and fanin/fanout interactively☆43Aug 14, 2026Updated last week
- QSDevsim☆16Jan 7, 2025Updated last year
- Benchmarks for Approximate Circuit Synthesis☆17Aug 2, 2020Updated 6 years ago
- An advanced circuit-based sat solver☆39Feb 24, 2025Updated last year
- verilog实现CLAHE(限制对比度自适应直方图均衡化)算法,并进行资源优化,含vivado综合工程。 // Verilog implementation of CLAHE (Contrast Limited Adaptive Histogram…☆20Apr 30, 2026Updated 3 months ago
- Codes of the paper Deformable Butterfly: A Highly Structured and Sparse Linear Transform.☆16Nov 1, 2021Updated 4 years ago
- An Automatic Synthesis Tool for PIM-based CNN Accelerators.☆17Feb 29, 2024Updated 2 years ago
- 面向 AI 编程 Agent 的开源形式验证技能库,聚焦 FPV、SVA、证明优化、TCL 脚本与可扩展的形式验证工作流。Open-source formal verification skills for AI coding agents, focused on FPV,…☆29Jul 27, 2026Updated 3 weeks ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- This repository implements a scaled-down LLaMA 2-like model on an ARM Cortex-M3 soft core, with a custom systolic array RTL module for ef…☆16Jun 25, 2025Updated last year
- Aztec code generator in Python☆12Apr 12, 2026Updated 4 months ago
- ☆56Jun 29, 2024Updated 2 years ago
- This is the Github Repo for the paper: MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis O…☆105Jul 29, 2025Updated last year
- TrojanSAINT: Gate-Level Netlist Sampling-Based Inductive Learning for Hardware Trojan Detection☆24Oct 3, 2023Updated 2 years ago
- A BDD-based Quantum Circuit Equivalence Checker☆15Jun 29, 2026Updated last month
- VLSI placement and routing tool☆15Dec 20, 2025Updated 8 months ago
- Gaussian Process and Uncertainty Quantification Summer School 2018☆31Dec 15, 2022Updated 3 years ago
- Library of example SystemC/TLM peripherals for various SoCs based on the SCS library☆16Jun 29, 2026Updated last month
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- A CORDIC implementation of square root Verilog calculation on Quartus Prime 16.0, with ability to simulate on ModelSim as well.☆19Jul 24, 2021Updated 5 years ago
- AIGER And-Inverter-Graph Library☆105Feb 17, 2026Updated 6 months ago
- A picture bed based on GitHub.☆14May 15, 2023Updated 3 years ago
- GDSII manipulation library☆17Dec 13, 2025Updated 8 months ago
- ☆12Sep 29, 2021Updated 4 years ago
- BitNet a4.8 Implementation in one file of pytorch☆26Jan 13, 2025Updated last year
- GNU toolchain for PULP and RISC-V☆14Mar 15, 2025Updated last year