BIGWJZ / VLSI-DSP-ReviewLinks
☆70Updated 4 years ago
Alternatives and similar repositories for VLSI-DSP-Review
Users that are interested in VLSI-DSP-Review are comparing it to the libraries listed below
Sorting:
- verilog实现TPU中的脉动阵列计算卷积的module☆124Updated 2 months ago
- Open IP in Hardware Description Language.☆24Updated last year
- 3×3脉动阵列乘法器☆45Updated 5 years ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆51Updated 11 months ago
- AXI协议规范中文翻译版☆153Updated 3 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder☆116Updated 12 years ago
- AXI总线连接器☆100Updated 5 years ago
- ☆41Updated 4 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆65Updated 11 months ago
- upgrade to e203 (a risc-v core)☆44Updated 4 years ago
- ☆34Updated 6 years ago
- Verilog program☆15Updated 4 years ago
- This is a series of quick start guide of Vitis HLS tool in Chinese. It explains the basic concepts and the most important optimize techni…☆22Updated 2 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆163Updated 5 years ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆41Updated 2 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- Some useful documents of Synopsys☆76Updated 3 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆49Updated 2 years ago
- ☆67Updated 9 years ago
- ☆43Updated 3 years ago
- ☆33Updated 10 months ago
- syn script for DC Compiler☆13Updated 3 years ago
- Collect some IC textbooks for learning.☆148Updated 2 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆217Updated 2 years ago
- ☆56Updated 2 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆83Updated 4 months ago
- An AXI4 crossbar implementation in SystemVerilog☆161Updated last month
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆21Updated 4 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 4 years ago