BIGWJZ / VLSI-DSP-ReviewLinks
☆70Updated 4 years ago
Alternatives and similar repositories for VLSI-DSP-Review
Users that are interested in VLSI-DSP-Review are comparing it to the libraries listed below
Sorting:
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆48Updated 10 months ago
- verilog实现TPU中的脉动阵列计算卷积的module☆119Updated last month
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆19Updated last year
- AXI总线连接器☆99Updated 5 years ago
- 3×3脉动阵列乘法器☆45Updated 5 years ago
- upgrade to e203 (a risc-v core)☆44Updated 4 years ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆40Updated 2 years ago
- Digital system design: Training lessons and exercise projects for students☆10Updated 2 years ago
- Some useful documents of Synopsys☆75Updated 3 years ago
- ☆21Updated last month
- Radix-4 1024 point fft in verilog☆10Updated 5 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆162Updated 5 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆37Updated last year
- verilog实现systolic array及配套IO☆8Updated 6 months ago
- AXI协议规范中文翻译版☆152Updated 2 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- Open IP in Hardware Description Language.☆24Updated last year
- syn script for DC Compiler☆13Updated 3 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆65Updated 10 months ago
- ☆39Updated 4 years ago
- ☆61Updated 2 years ago
- ☆16Updated last year
- FFT generator using Chisel☆60Updated 3 years ago
- ☆112Updated 4 years ago
- Convolutional Neural Network RTL-level Design☆58Updated 3 years ago
- This is a series of quick start guide of Vitis HLS tool in Chinese. It explains the basic concepts and the most important optimize techni…☆21Updated 2 years ago
- ☆34Updated 6 years ago
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆90Updated 3 years ago
- ☆44Updated last month
- Mirror of william_william/uvm-mcdf on Gitee☆23Updated 2 years ago