☆76Jul 28, 2020Updated 5 years ago
Alternatives and similar repositories for VLSI-DSP-Review
Users that are interested in VLSI-DSP-Review are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- 108下 計算機組織 Computer Organization 李毅郎☆11Feb 22, 2021Updated 5 years ago
- This repository integrates gem5 with Ramulator2, allowing gem5 to use Ramulator2 as its DRAM memory model. With the provided materials an…☆14Jun 7, 2025Updated last year
- DMA core compatible with AHB3-Lite☆13Mar 30, 2019Updated 7 years ago
- RTL code for the DPU chip designed for irregular graphs☆14May 30, 2022Updated 4 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆12Aug 22, 2021Updated 4 years ago
- 第四届全国大学生嵌入式比赛SoC☆12Apr 1, 2022Updated 4 years ago
- DMA controller for CNN accelerator☆14May 22, 2017Updated 9 years ago
- WISHBONE DMA/Bridge IP Core☆18Jul 17, 2014Updated 11 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- MAC system with IEEE754 compatibility☆14Nov 22, 2023Updated 2 years ago
- Verilog Ethernet Switch (layer 2)☆57Oct 18, 2023Updated 2 years ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated 2 years ago
- Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.☆17Dec 19, 2022Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Verilog Implementation of modular exponentiation using Montgomery multiplication☆37Sep 25, 2014Updated 11 years ago
- round robin arbiter☆78Jul 17, 2014Updated 11 years ago
- A hardware accelerator for General Matrix Multiply, developed in SystemC using ESP.☆20May 26, 2021Updated 5 years ago
- ☆82Jan 19, 2016Updated 10 years ago
- ☆19Updated this week
- A MATLAB function library containing encoders, decoders and weight enumerators for Reed-Muller codes.☆13Aug 19, 2023Updated 2 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆37Dec 22, 2023Updated 2 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆21May 4, 2017Updated 9 years ago
- DDR4 Simulation Project in System Verilog☆47Aug 18, 2014Updated 11 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- RTL implementation of TFlite FPGA accelerator and RISC-V controller. 3D Object Detection based on LiDAR Point Clouds.☆16Jun 24, 2026Updated last week
- A trivial riscv cpu with tomasulo algorithm implemented in Verilog HDL. Support out-of-order execution and pipline and can run in FPGA wi…☆16Jan 4, 2020Updated 6 years ago
- verification of simple axi-based cache☆19May 14, 2019Updated 7 years ago
- double_fpu_verilog☆21Jul 17, 2014Updated 11 years ago
- A custom coprocessor and SoC for hardware security experiments in electronics.☆12May 20, 2017Updated 9 years ago
- ☆16May 27, 2024Updated 2 years ago
- Reinforcement Learning Final Project☆13Dec 7, 2021Updated 4 years ago
- Voice Activity Detector based on MFCC features and DNN model☆30Jul 3, 2023Updated 2 years ago
- EE4415 Project : AES Verilog☆10Apr 25, 2019Updated 7 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Generic FIFO implementation with optional FWFT☆61May 27, 2020Updated 6 years ago
- This repository manages DSD lab code files.☆15Oct 29, 2021Updated 4 years ago
- 10_100_1000 Mbps tri-mode ethernet MAC☆11Jul 17, 2014Updated 11 years ago
- Professor: C.H. Yang☆10Aug 16, 2025Updated 10 months ago
- A DAG processor and compiler for a tree-based spatial datapath.☆16Aug 24, 2022Updated 3 years ago
- NCTU 2018 Spring Integrated Circuit Design Laboratory☆25Jun 25, 2018Updated 8 years ago
- openai-gym style RL benchmark for interconnection network congestion control study☆17May 12, 2022Updated 4 years ago