☆75Jul 28, 2020Updated 5 years ago
Alternatives and similar repositories for VLSI-DSP-Review
Users that are interested in VLSI-DSP-Review are comparing it to the libraries listed below
Sorting:
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- MAC system with IEEE754 compatibility☆13Nov 22, 2023Updated 2 years ago
- RTL code for the DPU chip designed for irregular graphs☆13May 30, 2022Updated 3 years ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated last year
- Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.☆17Dec 19, 2022Updated 3 years ago
- This repository integrates gem5 with Ramulator2, allowing gem5 to use Ramulator2 as its DRAM memory model. With the provided materials an…☆13Jun 7, 2025Updated 9 months ago
- 第四届全国大学生嵌入式比赛SoC☆11Apr 1, 2022Updated 3 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Aug 22, 2021Updated 4 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆37Dec 22, 2023Updated 2 years ago
- 108下 計算機組織 Computer Organization 李毅郎☆10Feb 22, 2021Updated 5 years ago
- DMA core compatible with AHB3-Lite☆10Mar 30, 2019Updated 6 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆12Aug 26, 2023Updated 2 years ago
- A hardware accelerator for General Matrix Multiply, developed in SystemC using ESP.☆16May 26, 2021Updated 4 years ago
- DMA controller for CNN accelerator☆14May 22, 2017Updated 8 years ago
- ☆15Sep 27, 2022Updated 3 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- Convert json descriptions of quant algorithms to verilog HDL.☆13Jul 3, 2020Updated 5 years ago
- RTL code of some arbitration algorithm☆15Aug 25, 2019Updated 6 years ago
- ☆19Oct 7, 2025Updated 5 months ago
- DDR4 Simulation Project in System Verilog☆44Aug 18, 2014Updated 11 years ago
- round robin arbiter☆78Jul 17, 2014Updated 11 years ago
- Artifacts for the "BBQ: A Fast and Scalable Integer Priority Queue for Hardware Packet Scheduling" paper that appears in NSDI '24.☆21Apr 23, 2024Updated last year
- WISHBONE DMA/Bridge IP Core☆18Jul 17, 2014Updated 11 years ago
- ☆74Jan 19, 2016Updated 10 years ago
- Voice Activity Detector based on MFCC features and DNN model☆29Jul 3, 2023Updated 2 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆20May 4, 2017Updated 8 years ago
- verification of simple axi-based cache☆18May 14, 2019Updated 6 years ago
- 异步FIFO的内部实现☆25Aug 26, 2018Updated 7 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆23May 20, 2019Updated 6 years ago
- EE577b-Course-Project☆19May 6, 2020Updated 5 years ago
- ☆21Feb 15, 2023Updated 3 years ago
- double_fpu_verilog☆21Jul 17, 2014Updated 11 years ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆33Aug 13, 2024Updated last year
- Synopsys Design compiler, VCS and Tetra-MAX☆19May 29, 2018Updated 7 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆30Nov 3, 2025Updated 4 months ago
- Generic FIFO implementation with optional FWFT☆61May 27, 2020Updated 5 years ago
- tpu-systolic-array-weight-stationary☆25May 7, 2021Updated 4 years ago
- AXI总线连接器☆105Mar 26, 2020Updated 5 years ago
- NCTU 2018 Spring Integrated Circuit Design Laboratory☆25Jun 25, 2018Updated 7 years ago