fengqzHD / gmIdNeoKitLinks
Gm Id Kit with GUI to Work with Matlab Data file similar to Prof. Boris Murmann's gm/ID Starter Kit
☆46Updated 5 years ago
Alternatives and similar repositories for gmIdNeoKit
Users that are interested in gmIdNeoKit are comparing it to the libraries listed below
Sorting:
- Python port of Prof. Boris Murmann's gm/ID Starter Kit☆54Updated 7 years ago
- A python3 gm/ID starter kit☆48Updated 9 months ago
- Read Spectre PSF files☆64Updated last week
- Python script for generating lookup tables for the gm/ID design methodology and much more ...☆89Updated last month
- Ancillary Material for the book "Systematic Design of Analog CMOS Circuits"☆138Updated this week
- This repo contains introduction of gm/id method and its application to some OTA design examples.☆14Updated last year
- repository for a bandgap voltage reference in SKY130 technology☆38Updated 2 years ago
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆67Updated last year
- A tiny Python package to parse spice raw data files.☆53Updated 2 years ago
- This library is an attempt to make transistor sizing for Analog design less painful.☆18Updated last year
- Sandbox for experimenting with Ngspice and open PDKs in Google Colab☆21Updated last year
- Gm over Id methodology☆23Updated 3 years ago
- This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A c…☆11Updated 5 years ago
- Advanced integrated circuits 2023☆30Updated last year
- Parametric layout generator for digital, analog and mixed-signal integrated circuits☆54Updated this week
- A 10bit SAR ADC in Sky130☆23Updated 2 years ago
- BAG framework☆29Updated 5 months ago
- COCOA: Collaborative Compendium on Analog Integrated Circuits☆17Updated 2 months ago
- Solve one design problem each day for a month☆43Updated 2 years ago
- Cadence SKILL utilities that have boosted my productivity considerably for 10+ years.☆45Updated this week
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆31Updated 3 years ago
- BAG2 workspace for fake PDK (cds_ff_mpt)☆55Updated 5 years ago
- Delta-Sigma modulator (DSM) for fractional phase locked loop.☆28Updated 4 years ago
- MATLAB toolbox for interfacing with the Cadence Virtuoso IC Design System☆30Updated 8 years ago
- How to correctly write a flicker-noise model for RF simulation.☆21Updated 2 years ago
- Circuit Automatic Characterization Engine☆49Updated 4 months ago
- Python library for SerDes modelling☆69Updated 10 months ago
- Verilog-A simulation models☆72Updated last week
- PLL Designs on Skywater 130nm MPW☆20Updated last year
- ☆79Updated 4 months ago