Algorithm to hardware compilation tools (e.g. C to VHDL).
☆46Nov 30, 2025Updated 9 months ago
Alternatives and similar repositories for ahir
Users that are interested in ahir are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- vhdl related contents☆11Apr 27, 2020Updated 6 years ago
- Library for reading Xilinx .bit bitstream file headers with metadata extraction☆14Apr 7, 2026Updated 4 months ago
- Recipe for FPGA cooking☆12Mar 15, 2019Updated 7 years ago
- Hardware Description Language Translator☆19Aug 7, 2026Updated 3 weeks ago
- ☆16May 9, 2022Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- general-cores☆21Jul 16, 2025Updated last year
- VHDL ieee_proposed library, imported as is. See also https://github.com/FPHDL/fphdl☆12Aug 26, 2016Updated 10 years ago
- All the projects and assignments done as part of VLSI course.☆21Sep 23, 2020Updated 5 years ago
- ☆29May 5, 2022Updated 4 years ago
- ☆18Sep 16, 2020Updated 5 years ago
- Network on Chip for MPSoC☆29Aug 7, 2026Updated 3 weeks ago
- Repository containing the DSP gateware cores☆14Mar 9, 2026Updated 5 months ago
- The Verilog source code for DRUM approximate multiplier.☆32May 4, 2023Updated 3 years ago
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Common code library☆15Feb 3, 2018Updated 8 years ago
- Implementation of FM (frequency modulation) radio transmitter in FPGA Altera Cyclone III.☆14May 16, 2016Updated 10 years ago
- C# projects that use ANTLR4 library to analyse VHDL and Verilog code☆11Feb 28, 2015Updated 11 years ago
- Example designs for using Ethernet FMC without a processor (ie. state machine based)☆35Jul 7, 2026Updated last month
- A configuration controller solution allowing a Zynq device to configure downstream FPGAs☆14Oct 5, 2015Updated 10 years ago
- VHDL package to provide C-like string formatting☆15May 6, 2022Updated 4 years ago
- Neural Turing Machine for a Multi-Processor System on Chip verified with UVM/OSVVM/FV☆12Aug 9, 2026Updated 3 weeks ago
- Hardware and script files related to dynamic partial reconfiguration☆11Mar 16, 2018Updated 8 years ago
- A vhdl package for reading and writing bitmap files.☆12Jan 9, 2018Updated 8 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- AXI DMA Check: A utility to measure DMA speeds in simulation☆16Jan 22, 2025Updated last year
- SIMPLE MAGIC: Synthesis and In-memory MaPping of Logic Execution for Memristor Aided loGIC☆15Jan 23, 2020Updated 6 years ago
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆19Mar 30, 2025Updated last year
- Direct Access Memory for MPSoC☆13Aug 7, 2026Updated 3 weeks ago
- ARCH hardware description language and compiler☆74Updated this week
- This repository is about video compression, and more specifically about the motion estimation block (ME block) of a video encoder. It is …☆13Sep 14, 2020Updated 5 years ago
- IoT Platform is a software to manage large scale deployment of IoT devices and to process big data generated by them.☆18Oct 1, 2018Updated 7 years ago
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆14Aug 9, 2026Updated 3 weeks ago
- ☆11Jan 25, 2023Updated 3 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Open source FPGA cores for digital signal processing (push mirror from gitlab.com/theseus-cores/theseus-cores)☆16Aug 16, 2021Updated 5 years ago
- 4th RISC-V Workshop Tutorials☆13Jul 19, 2016Updated 10 years ago
- Accelerating a Classic 3D Video Game (The DOOM) on Heterogeneous Reconfigurable MPSoCs☆21Jun 4, 2020Updated 6 years ago
- SHA-1,SHA-256,SHA-512 Secure Hash Generator written in VHDL(RTL) for FPGA(Xilinx and Altera).☆12Oct 14, 2017Updated 8 years ago
- Heston implementation for Zynq with Vivado HLS☆16Jun 30, 2015Updated 11 years ago
- A ZipCPU SoC for the Nexys Video board supporting video functionality☆21Nov 13, 2024Updated last year
- high level VHDL floating point library for synthesis in fpga☆18Dec 18, 2025Updated 8 months ago