QianfengClarkShen / GULF-StreamLinks
100G Udp Link For axi Stream
☆13Updated last year
Alternatives and similar repositories for GULF-Stream
Users that are interested in GULF-Stream are comparing it to the libraries listed below
Sorting:
- understanding of cocotb (In Chinese Only)☆17Updated last year
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆54Updated 3 years ago
- ☆19Updated 3 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- 10G Low Latency Ethernet☆54Updated last year
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆54Updated last year
- Reed Solomon Encoder and Decoder Digital IP☆21Updated 4 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆42Updated last year
- Generate testbench for your verilog module.☆38Updated 7 years ago
- Quick Example how to generate an custom AXI4 IP with AXI4-Full interface (burst) for the Zynq (ZedBoard)☆43Updated 7 years ago
- This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.☆84Updated last year
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆64Updated 9 months ago
- Verilog RTL Design☆39Updated 3 years ago
- A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+☆39Updated 2 years ago
- Open source FPGA-based NIC and platform for in-network compute☆63Updated 7 months ago
- 2D Systolic Array Multiplier☆15Updated last year
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆62Updated last year
- Verilog Content Addressable Memory Module☆107Updated 3 years ago
- R22SDF FFT VLSI/FPGA investigate and implementation☆15Updated 3 years ago
- Generic FIFO implementation with optional FWFT☆57Updated 5 years ago
- The Strathclyde RFSoC Studio Installer for PYNQ.☆32Updated 2 years ago
- RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.☆27Updated last year
- RTL Verilog library for various DSP modules☆88Updated 3 years ago
- A PYNQ overlay demonstrating the Xilinx RFSoC SD-FEC☆13Updated 2 years ago
- A 32 point radix-2 FFT module written in Verilog☆23Updated 4 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆54Updated last year
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- UART -> AXI Bridge☆61Updated 3 years ago
- A 2D convolution hardware implementation written in Verilog☆47Updated 4 years ago
- Verilog based BCH encoder/decoder☆120Updated 2 years ago