QianfengClarkShen / GULF-Stream
100G Udp Link For axi Stream
☆12Updated last year
Alternatives and similar repositories for GULF-Stream:
Users that are interested in GULF-Stream are comparing it to the libraries listed below
- understanding of cocotb (In Chinese Only)☆16Updated last year
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- All digital PLL☆28Updated 7 years ago
- The Strathclyde RFSoC Studio Installer for PYNQ.☆31Updated 2 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆43Updated 2 years ago
- Generic FIFO implementation with optional FWFT☆57Updated 4 years ago
- Verilog RTL Design☆35Updated 3 years ago
- Reed Solomon Encoder and Decoder Digital IP☆19Updated 4 years ago
- 通过调试ADRV9009和AD9371对jesd204b知识点作进一步学习和总结☆22Updated 5 years ago
- 10G Low Latency Ethernet☆53Updated last year
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆53Updated 3 years ago
- Open source FPGA-based NIC and platform for in-network compute☆62Updated 6 months ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆41Updated last year
- Gigabit MAC + UDP/TCP/IP offload Engine☆31Updated 5 years ago
- Verilog digital signal processing components☆133Updated 2 years ago
- Ethernet interface modules for Cocotb☆63Updated last year
- ☆19Updated 3 years ago
- Ethernet Example Projects targeting the Xilinx ZCU102 evaluation board. This repository replaces XAPP1305.☆63Updated 2 months ago
- RTL Verilog library for various DSP modules☆88Updated 3 years ago
- Interface Protocol in Verilog☆49Updated 5 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆66Updated 5 months ago
- 100 MB/s Ethernet MAC Layer Switch☆14Updated 10 years ago
- ☆25Updated 3 years ago
- Single Port RAM, Dual Port RAM, FIFO☆24Updated 2 years ago
- Ethernet switch implementation written in Verilog☆47Updated last year
- UDP-IP stack accelerator and is able to send and receive data through Ethernet link☆21Updated 2 months ago
- Hardware Assisted IEEE 1588 IP Core☆28Updated 10 years ago
- Quick Example how to generate an custom AXI4 IP with AXI4-Full interface (burst) for the Zynq (ZedBoard)☆43Updated 7 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆56Updated 2 years ago
- AES hardware engine for Xilinx Zynq platform☆30Updated 3 years ago