Alternatives and similar repositories for pynq_dev:

Users that are interested in pynq_dev are comparing it to the libraries listed below

• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆29Updated 8 years ago
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆16Updated 5 years ago
• AEW2015 / PYNQ_PR_Overlay
  Adding PR to the PYNQ Overlay
  ☆17Updated 7 years ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 6 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆33Updated last month
• patocarr / axi-traffic-gen
  File editor for the Xilinx AXI Traffic Generator IP
  ☆16Updated 4 months ago
• hgomersall / Ovenbird
  A tool for merging the MyHDL workflow with Vivado
  ☆20Updated 4 years ago
• taichi-ishitani / rggen
  This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
  ☆17Updated 5 years ago
• thinkoco / systemverilog-python
  Systemverilog DPI-C call Python function
  ☆22Updated 4 years ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆43Updated 9 years ago
• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆28Updated 2 years ago
• Elphel / eddr3
  mirror of https://git.elphel.com/Elphel/eddr3
  ☆40Updated 7 years ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆32Updated 7 years ago
• paulscherrerinstitute / VivadoScripting
  Python Utilities to use Xilinx Vivado Tools from Python Scripts
  ☆17Updated 4 years ago
• mcjtag / axis-uart
  AXI Stream UART (verilog)
  ☆11Updated 5 years ago
• amiq-consulting / physical_coding_library
  ☆18Updated 8 years ago
• Architech-Silica / Zynq-Configuration-Controller
  A configuration controller solution allowing a Zynq device to configure downstream FPGAs
  ☆14Updated 9 years ago
• fpgadeveloper / microzed-axi-dma
  Demonstration of the AXI DMA engine on the MicroZed
  ☆26Updated 4 years ago
• h-nasiri / Zynq-Linux-DMA
  DMA enabled Zynq PS-PL communication to implement high throughput data transfer between Linux applications and user IP core.
  ☆39Updated 8 years ago
• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 10 years ago
• aquaxis / gemac
  Gigabit MAC + UDP/TCP/IP offload Engine
  ☆31Updated 5 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆56Updated 4 years ago
• ikwzm / ZynqMP-FPGA-Ubuntu18.04-Ultra96
  Ubuntu 18.04 Desktop for Ultra96/Ultra96-V2
  ☆19Updated 4 years ago
• delhatch / Zynq_UDP
  Transfer data over UDP with a Zedboard. This is an example project that transmits and receives data over UDP.
  ☆25Updated 4 years ago
• fpgadeveloper / ethernet-fmc-axi-eth
  Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks
  ☆64Updated 4 months ago
• sdnellen / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆15Updated 3 months ago
• warclab / zycap
  Zynq PR Management
  ☆12Updated 8 years ago
• umaurmi / OPENCL_EXAMPLES_ZEDBOARD
  This repository contains a set of examples of opencl code that can run on the zedboard zynq all programmable soc.
  ☆16Updated 9 years ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆40Updated 6 years ago
• Xilinx / PYNQ-Networking
  Networking Overlay on PYNQ
  ☆48Updated 6 years ago