Alternatives and similar repositories for rapidstream-tapa:

Users that are interested in rapidstream-tapa are comparing it to the libraries listed below

• UCLA-VAST / AutoBridge
  [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
  ☆123Updated 2 years ago
• arc-research-lab / CHARM
  CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture
  ☆129Updated last month
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆118Updated 2 weeks ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆85Updated 3 months ago
• UCLA-VAST / AutoSA
  AutoSA: Polyhedral-Based Systolic Array Compiler
  ☆210Updated 2 years ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆84Updated 4 months ago
• lana555 / dynamatic
  ☆86Updated 11 months ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆77Updated 6 months ago
• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆58Updated last month
• cornell-zhang / rosetta
  Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs
  ☆165Updated last year
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆79Updated 6 years ago
• pnnl / OpenCGRA
  OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.
  ☆140Updated last year
• pnnl / soda-opt
  ☆40Updated last week
• breagen / MachSuite
  Benchmarks for Accelerator Design and Customized Architectures
  ☆117Updated 4 years ago
• georgia-tech-synergy-lab / SIGMA
  RTL implementation of Flex-DPE.
  ☆97Updated 5 years ago
• ehw-fit / evoapproxlib
  Library of approximate arithmetic circuits
  ☆53Updated 2 years ago
• makslevental / openhls
  PyTorch model to RTL flow for low latency inference
  ☆125Updated 11 months ago
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆67Updated 5 years ago
• vaughnbetz / COFFE
  ☆40Updated 5 months ago
• tancheng / CGRA-Mapper
  An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.
  ☆59Updated 2 months ago
• UCLA-VAST / RapidStream
  [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
  ☆119Updated 2 years ago
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆42Updated this week
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆189Updated 3 weeks ago
• UCLA-VAST / FlexCNN
  ☆71Updated 2 years ago
• spcl / hls_tutorial_examples
  Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
  ☆199Updated 3 years ago
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆72Updated 2 weeks ago
• UIUC-ChenLab / scalehls
  A scalable High-Level Synthesis framework on MLIR
  ☆245Updated 9 months ago
• Xilinx / logicnets
  ☆83Updated 8 months ago
• sharc-lab / FlowGNN
  A dataflow architecture for universal graph neural network inference via multi-queue streaming.
  ☆70Updated 2 years ago
• SingularityKChen / dl_accelerator
  Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions
  ☆178Updated 4 years ago