rapidstream-org / rapidstream-tapaLinks
RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.
☆172Updated this week
Alternatives and similar repositories for rapidstream-tapa
Users that are interested in rapidstream-tapa are comparing it to the libraries listed below
Sorting:
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆122Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆92Updated 8 months ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆165Updated last year
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆132Updated last week
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆143Updated this week
- AutoSA: Polyhedral-Based Systolic Array Compiler☆221Updated 2 years ago
- An integrated CGRA design framework☆89Updated 3 months ago
- ☆86Updated last year
- An Open-Source Tool for CGRA Accelerators☆67Updated 2 months ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆153Updated 2 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆124Updated 5 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆79Updated 11 months ago
- ☆45Updated 3 weeks ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆72Updated 6 years ago
- Vitis HLS Library for FINN☆198Updated 3 weeks ago
- ☆55Updated 3 months ago
- Library of approximate arithmetic circuits☆55Updated 2 years ago
- Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…☆110Updated last week
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆38Updated last month
- RTL implementation of Flex-DPE.☆103Updated 5 years ago
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆200Updated 3 years ago
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆319Updated 5 months ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- Automatic generation of FPGA-based learning accelerators for the neural network family☆66Updated 5 years ago
- A DSL for Systolic Arrays☆79Updated 6 years ago
- ☆94Updated last year
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆73Updated 2 weeks ago
- Fast and accurate DRAM power and energy estimation tool☆165Updated 2 weeks ago
- An integrated power, area, and timing modeling framework for multicore and manycore architectures☆187Updated 4 years ago