rapidstream-org / rapidstream-tapa
RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.
☆156Updated this week
Related projects ⓘ
Alternatives and complementary repositories for rapidstream-tapa
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆121Updated last year
- AutoSA: Polyhedral-Based Systolic Array Compiler☆200Updated last year
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆113Updated last week
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆80Updated last month
- ☆87Updated 8 months ago
- An integrated CGRA design framework☆83Updated last week
- An Open-Source Tool for CGRA Accelerators☆57Updated 3 months ago
- Benchmarks for Accelerator Design and Customized Architectures☆116Updated 4 years ago
- CHARM: Composing Heterogeneous Accelerators on Versal ACAP Architecture☆124Updated 2 weeks ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆135Updated last year
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆158Updated last year
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆71Updated 3 months ago
- ☆37Updated 4 months ago
- A scalable High-Level Synthesis framework on MLIR☆228Updated 6 months ago
- Release of stream-specialization software/hardware stack.☆116Updated last year
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆56Updated this week
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆64Updated 5 years ago
- A DSL for Systolic Arrays☆78Updated 5 years ago
- Template-based Reconfigurable Architecture Modeling Framework☆13Updated 2 years ago
- Vitis HLS Library for FINN☆181Updated this week
- Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…☆96Updated last year
- PyTorch model to RTL flow for low latency inference☆121Updated 8 months ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆117Updated last year
- HLS-based Graph Processing Framework on FPGAs☆139Updated 2 years ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆260Updated 3 weeks ago
- A Chisel RTL generator for network-on-chip interconnects☆177Updated this week
- Library of approximate arithmetic circuits☆51Updated 2 years ago
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆31Updated this week
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆65Updated this week
- DRA+RISC-V Exploration Framework☆16Updated 10 months ago