rapidstream-org / rapidstream-tapa
RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.
☆167Updated this week
Alternatives and similar repositories for rapidstream-tapa:
Users that are interested in rapidstream-tapa are comparing it to the libraries listed below
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆122Updated 2 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆123Updated last week
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆164Updated last year
- ☆86Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆90Updated 6 months ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆218Updated 2 years ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆138Updated this week
- An integrated CGRA design framework☆87Updated last month
- An Open-Source Tool for CGRA Accelerators☆64Updated last week
- ☆44Updated last month
- ☆41Updated 7 months ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆149Updated 2 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆78Updated 8 months ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆122Updated 2 years ago
- Vitis HLS Library for FINN☆192Updated this week
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆71Updated 5 years ago
- RTL implementation of Flex-DPE.☆99Updated 5 years ago
- ☆49Updated last month
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆67Updated last week
- Benchmarks for Accelerator Design and Customized Architectures☆121Updated 5 years ago
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆34Updated 2 weeks ago
- Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…☆106Updated last year
- HLS-based Graph Processing Framework on FPGAs☆144Updated 2 years ago
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆199Updated 3 years ago
- A DSL for Systolic Arrays☆78Updated 6 years ago
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆29Updated 3 weeks ago
- Library of approximate arithmetic circuits☆53Updated 2 years ago
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆24Updated last year
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆189Updated 4 years ago
- ☆35Updated 3 weeks ago