☆72Feb 14, 2023Updated 3 years ago
Alternatives and similar repositories for verilator_basics
Users that are interested in verilator_basics are comparing it to the libraries listed below
Sorting:
- Little RISC-V 3-stage Pipeline CPU☆16Jun 14, 2021Updated 4 years ago
- ☆12May 21, 2020Updated 5 years ago
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆13Oct 19, 2024Updated last year
- SGMII☆13Jul 17, 2014Updated 11 years ago
- Quickstart guide on Icarus Verilog.☆41Jun 18, 2020Updated 5 years ago
- ☆119Nov 11, 2025Updated 4 months ago
- A ZipCPU SoC for the Nexys Video board supporting video functionality☆20Nov 13, 2024Updated last year
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 6 years ago
- ☆21Mar 30, 2023Updated 2 years ago
- ePIC (Embedded PIC) example: kernel and relocatable loadable app☆14Oct 27, 2023Updated 2 years ago
- asynchronous fifo based on verilog☆14Apr 14, 2022Updated 3 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆37Jun 21, 2023Updated 2 years ago
- A tiny 3-stage RISC-V core written in Chisel.☆16Apr 14, 2023Updated 2 years ago
- A transaction level model of a PCI express root complex implemented in systemc☆23Jun 16, 2014Updated 11 years ago
- A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆31Feb 10, 2020Updated 6 years ago
- ☆13Jan 16, 2026Updated 2 months ago
- GPTPU for SC 2021☆53Mar 22, 2023Updated 2 years ago
- A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.☆18Aug 27, 2025Updated 6 months ago
- Example of Python and PyTest powered workflow for a HDL simulation☆15Jan 17, 2021Updated 5 years ago
- A tool to run litmus tests on bare-metal hardware☆13Mar 13, 2017Updated 9 years ago
- 21Summer-VE370-Intro-to-Computer-Organization-Projects: -Project1: RISC-V Assembly, simluating c code. -Project2: 1.RISC-V64 sin…☆14Apr 11, 2023Updated 2 years ago
- Common SystemVerilog RTL modules for RgGen☆16Feb 5, 2026Updated last month
- Public repository to host our Checker IP written in SVA that is ported to run on open-source Verilator.☆12Mar 31, 2023Updated 2 years ago
- ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.☆39Feb 22, 2026Updated 3 weeks ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆37Mar 11, 2026Updated last week
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Mar 13, 2026Updated last week
- Learn UVM by small projects☆18Aug 31, 2021Updated 4 years ago
- The official website of One Student One Chip project.☆11Feb 5, 2026Updated last month
- This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…☆17Sep 29, 2024Updated last year
- ☆21Mar 18, 2022Updated 4 years ago
- Automated UVM testbench generator from Verilog RTL with optional LLM integration for advanced logic creation.☆19Feb 24, 2026Updated 3 weeks ago
- Learn systemC with examples☆131Dec 21, 2022Updated 3 years ago
- ☆13Aug 22, 2022Updated 3 years ago
- A reliable, real-time subsystem for the Carfield SoC☆19Dec 2, 2025Updated 3 months ago
- ☆17Feb 13, 2021Updated 5 years ago
- understanding of cocotb （In Chinese Only）☆21Jun 10, 2025Updated 9 months ago
- GF180 ASIC tapeout of a 2x2 MAC with DFT infrastructure☆49Jan 13, 2026Updated 2 months ago
- ☆14Apr 29, 2024Updated last year
- A repository for SystemC Learning examples☆74Oct 25, 2022Updated 3 years ago