Alternatives and similar repositories for verilator_basics

Users that are interested in verilator_basics are comparing it to the libraries listed below

• chipsalliance / uvm-verilator
  ☆96Updated last year
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆84Updated last week
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆57Updated 3 years ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆211Updated last week
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆165Updated this week
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆64Updated last month
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆151Updated 7 months ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆62Updated last year
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆62Updated last year
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆94Updated 4 years ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆109Updated 2 years ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆68Updated 11 months ago
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆71Updated 2 weeks ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆115Updated this week
• tom01h / zero-riscy
  zero-riscy CPU Core
  ☆16Updated 7 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆51Updated last year
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆157Updated last week
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆55Updated last year
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆112Updated last week
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆105Updated last month
• maltanar / axi-in-chisel
  Examples for creating AXI-interfaced peripherals in Chisel
  ☆76Updated 9 years ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆61Updated 5 months ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆89Updated 3 years ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆121Updated 4 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆40Updated 4 years ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆94Updated 3 weeks ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆57Updated last week
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆68Updated 7 months ago
• pulp-platform / fpu
  ☆51Updated 6 years ago