☆75Feb 14, 2023Updated 3 years ago
Alternatives and similar repositories for verilator_basics
Users that are interested in verilator_basics are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Little RISC-V 3-stage Pipeline CPU☆16Jun 14, 2021Updated 5 years ago
- ☆13May 21, 2020Updated 6 years ago
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆18Oct 19, 2024Updated last year
- SGMII☆14Jul 17, 2014Updated 11 years ago
- Quickstart guide on Icarus Verilog.☆42Jun 18, 2020Updated 5 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- ☆128Nov 11, 2025Updated 7 months ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 6 years ago
- A ZipCPU SoC for the Nexys Video board supporting video functionality☆20Nov 13, 2024Updated last year
- ☆21Mar 30, 2023Updated 3 years ago
- ePIC (Embedded PIC) example: kernel and relocatable loadable app☆14Oct 27, 2023Updated 2 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆38Jun 21, 2023Updated 2 years ago
- A tiny 3-stage RISC-V core written in Chisel.☆16Apr 14, 2023Updated 3 years ago
- A transaction level model of a PCI express root complex implemented in systemc☆23Jun 16, 2014Updated 11 years ago
- A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆31Feb 10, 2020Updated 6 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- ☆14Apr 28, 2026Updated last month
- A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.☆18Aug 27, 2025Updated 9 months ago
- Example of Python and PyTest powered workflow for a HDL simulation☆15Jan 17, 2021Updated 5 years ago
- A tool to run litmus tests on bare-metal hardware☆13Mar 13, 2017Updated 9 years ago
- 21Summer-VE370-Intro-to-Computer-Organization-Projects: -Project1: RISC-V Assembly, simluating c code. -Project2: 1.RISC-V64 sin…☆14Apr 11, 2023Updated 3 years ago
- Common SystemVerilog RTL modules for RgGen☆16Feb 5, 2026Updated 4 months ago
- Public repository to host our Checker IP written in SVA that is ported to run on open-source Verilator.☆12Mar 31, 2023Updated 3 years ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆39Jun 7, 2026Updated last week
- ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.☆39Feb 22, 2026Updated 3 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- The official website of One Student One Chip project.☆12Feb 5, 2026Updated 4 months ago
- This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…☆18Sep 29, 2024Updated last year
- ☆21Mar 18, 2022Updated 4 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆68Updated this week
- ☆13Aug 22, 2022Updated 3 years ago
- Learn UVM by small projects☆22Aug 31, 2021Updated 4 years ago
- Learn systemC with examples☆137Dec 21, 2022Updated 3 years ago
- ☆17Feb 13, 2021Updated 5 years ago
- understanding of cocotb (In Chinese Only)☆22Jun 10, 2025Updated last year
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- ☆14Apr 29, 2024Updated 2 years ago
- A repository for SystemC Learning examples☆74Oct 25, 2022Updated 3 years ago
- Automated UVM testbench generator from Verilog RTL with optional LLM integration for advanced logic creation.☆27Feb 24, 2026Updated 3 months ago
- Determines the modules declared and instantiated in a SystemVerilog file☆51Sep 23, 2024Updated last year
- Qemu tracing plugin using SimPoints☆17Sep 12, 2024Updated last year
- GF180 ASIC tapeout of a 2x2 MAC with DFT infrastructure☆57Apr 27, 2026Updated last month
- A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …☆121Oct 31, 2024Updated last year