n-kremeris / verilator_basics

Related projects ⓘ

Alternatives and complementary repositories for verilator_basics

• chipsalliance / uvm-verilator
  ☆75Updated last year
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆60Updated this week
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆47Updated 2 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆49Updated 10 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆138Updated this week
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆106Updated 3 years ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆93Updated this week
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆35Updated 2 years ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆76Updated 2 months ago
• ee-uet / UETRV-PCore
  Linux Capable 32-bit RISC-V based SoC in System Verilog
  ☆56Updated last week
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆43Updated 2 years ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆108Updated this week
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆59Updated last month
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆32Updated 3 years ago
• omega-rg / Cache-Controller
  Two Level Cache Controller implementation in Verilog HDL
  ☆36Updated 4 years ago
• tom01h / zero-riscy
  zero-riscy CPU Core
  ☆14Updated 6 years ago
• ucb-ucie / uciedigital
  Pure digital components of a UCIe controller
  ☆48Updated 2 weeks ago
• maltanar / axi-in-chisel
  Examples for creating AXI-interfaced peripherals in Chisel
  ☆71Updated 9 years ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆75Updated this week
• martinriis / RISC-V-Vector-Processor
  256-bit vector processor based on the RISC-V vector (V) extension
  ☆28Updated 3 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆48Updated 5 months ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆107Updated last year
• accellera / uvm
  ☆42Updated 8 years ago
• aignacio / nox
  RISC-V Nox core
  ☆61Updated 3 months ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆110Updated 4 years ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆46Updated 2 years ago
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆125Updated 2 years ago
• schoeberl / chisel-empty
  An almost empty chisel project as a starting point for hardware design
  ☆29Updated last year
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆67Updated 6 months ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆62Updated 5 months ago