Alternatives and similar repositories for ghdl-language-server

Users that are interested in ghdl-language-server are comparing it to the libraries listed below

• suoto / hdl_checker
  Repurposing existing HDL tools to help writing better code
  ☆217Updated last year
• tree-sitter / tree-sitter-verilog
  SystemVerilog grammar for tree-sitter
  ☆109Updated 11 months ago
• imc-trading / svlangserver
  ☆120Updated last year
• jeremiah-c-leary / vhdl-style-guide
  Style guide enforcement for VHDL
  ☆225Updated 3 weeks ago
• VHDL-LS / rust_hdl_vscode
  VHDL Language Support for VSCode
  ☆69Updated 7 months ago
• VHDL-LS / rust_hdl
  A fast VHDL language server and analysis library written in Rust
  ☆433Updated 2 weeks ago
• alemuller / tree-sitter-vhdl
  VHDL grammar for tree-sitter
  ☆31Updated last year
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆64Updated last year
• dalance / svlint
  SystemVerilog linter
  ☆364Updated last month
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆246Updated last year
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆235Updated last month
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆84Updated last year
• VHDL / awesome-vhdl
  A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.
  ☆82Updated 5 years ago
• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆276Updated last year
• hdl / awesome
  A curated list of awesome resources for HDL design and verification
  ☆163Updated last week
• OSVVM / Documentation
  OSVVM Documentation
  ☆36Updated this week
• hdl / containers
  Building and deploying container images for open source electronic design automation (EDA)
  ☆116Updated last year
• vivekmalneedi / veridian
  A SystemVerilog Language Server
  ☆187Updated 6 months ago
• kevinpt / symbolator
  HDL symbol generator
  ☆195Updated 2 years ago
• pulp-platform / bender
  A dependency management tool for hardware projects.
  ☆332Updated this week
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆72Updated last year
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆51Updated this week
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 9 months ago
• chipsalliance / homebrew-verible
  ☆22Updated 3 months ago
• pieter3d / simview
  ☆85Updated 3 weeks ago
• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆48Updated 10 months ago
• chaseruskin / orbit
  Package manager and build system for VHDL, Verilog, and SystemVerilog
  ☆57Updated last week
• Isotel / mixedsim
  Hardware Design Tool - Mixed Signal Simulation with Verilog
  ☆87Updated 10 months ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆422Updated last month
• dalance / svls
  SystemVerilog language server
  ☆543Updated 3 weeks ago