Alternatives and similar repositories for ghdl-language-server:

Users that are interested in ghdl-language-server are comparing it to the libraries listed below

• suoto / hdl_checker
  Repurposing existing HDL tools to help writing better code
  ☆200Updated 8 months ago
• imc-trading / svlangserver
  ☆106Updated 8 months ago
• VHDL-LS / rust_hdl_vscode
  VHDL Language Support for VSCode
  ☆59Updated last week
• tree-sitter / tree-sitter-verilog
  SystemVerilog grammar for tree-sitter
  ☆96Updated 3 months ago
• vivekmalneedi / veridian
  A SystemVerilog Language Server
  ☆154Updated last month
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆209Updated 3 months ago
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆225Updated 4 months ago
• hdl / awesome
  A curated list of awesome resources for HDL design and verification
  ☆144Updated last week
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated 11 months ago
• kevinpt / symbolator
  HDL symbol generator
  ☆187Updated 2 years ago
• OSVVM / Documentation
  OSVVM Documentation
  ☆33Updated this week
• pieter3d / simview
  ☆77Updated 11 months ago
• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆42Updated last month
• VHDL / awesome-vhdl
  A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.
  ☆80Updated 5 years ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆177Updated this week
• jeremiah-c-leary / vhdl-style-guide
  Style guide enforcement for VHDL
  ☆198Updated 3 weeks ago
• dalance / svlint
  SystemVerilog linter
  ☆334Updated last month
• VHDL-LS / rust_hdl
  ☆372Updated last month
• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆272Updated 10 months ago
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆73Updated 2 months ago
• wavedrom / vcdrom
  VCD viewer
  ☆84Updated 3 months ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆381Updated 2 months ago
• dalance / svls
  SystemVerilog language server
  ☆492Updated this week
• suoto / vim-hdl
  Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)
  ☆60Updated 3 years ago
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆81Updated 7 months ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆65Updated 2 weeks ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆126Updated 3 weeks ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆54Updated 4 months ago
• wavedrom / cli
  CLI for WaveDrom
  ☆61Updated last year
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆369Updated last month