Alternatives and similar repositories for verilog-ext

Users that are interested in verilog-ext are comparing it to the libraries listed below

• gmlarumbe / vhdl-ext
  VHDL Extensions for Emacs
  ☆35Updated 3 weeks ago
• gmlarumbe / verilog-ts-mode
  Emacs Verilog Tree-sitter Major-mode
  ☆12Updated 2 weeks ago
• veripool / verilog-mode
  Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
  ☆272Updated last month
• embed-me / vunit-mode
  A simple Emacs minor mode for VUnit
  ☆12Updated 2 months ago
• gmlarumbe / fpga
  fpga.el - FPGA & ASIC Utils for Emacs
  ☆22Updated last month
• dallingham / verilog-mode-snippets
  A set of yasnippets for emacs that assist with SystemVerilog
  ☆11Updated 13 years ago
• imc-trading / svlangserver
  ☆119Updated last year
• suoto / hdl_checker
  Repurposing existing HDL tools to help writing better code
  ☆217Updated last year
• jwwebbopen / SystemVerilogTools
  Tools for SystemVerilog development.
  ☆15Updated 7 years ago
• Remillard / VHDL-Mode
  A package for Sublime Text that aids coding in the VHDL language.
  ☆42Updated 2 years ago
• wyvernSemi / eccExamples
  Error correction and detection example Verilog (hamming and Reed-Solomon) to accompany presentation material
  ☆11Updated last year
• cluelogic / cluelib
  A generic class library in SystemVerilog
  ☆84Updated 4 years ago
• svunit / svunit
  ☆206Updated 6 months ago
• vim-scripts / verilog_emacsauto.vim
  verilog filetype plugin to enable emacs verilog-mode autos
  ☆17Updated 3 years ago
• mxg / topaz
  ☆24Updated last year
• mxg / svx
  SystemVerilog Extension Library -- a library of utilities for generic programming and increased productivity
  ☆30Updated last year
• csantosb / vhdl-tools
  Easier navigation of VHDL sources
  ☆12Updated 5 years ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆253Updated 7 months ago
• ghdl / ghdl-language-server
  Language server based on ghdl
  ☆97Updated 4 months ago
• amiq-consulting / amiq_blog
  Code snippets from articles published on www.amiq.com/consulting/blog
  ☆36Updated last year
• paradigm-works / uvmtb_template
  Simple UVM testbench development using the uvmtb_template files
  ☆17Updated 7 months ago
• nosnhojn / uvm-utest
  ☆18Updated 10 years ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆416Updated last week
• rggen / rggen
  Code generation tool for control and status registers
  ☆421Updated 3 weeks ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆450Updated 2 months ago
• verilator / verilator-announce
  Announcements related to Verilator
  ☆39Updated 5 years ago
• tree-sitter / tree-sitter-verilog
  SystemVerilog grammar for tree-sitter
  ☆108Updated 10 months ago
• jwwebbopen / VerilogTools
  Tools for Verilog HDL development.
  ☆10Updated 13 years ago
• accellera / uvm
  ☆56Updated 9 years ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆139Updated last year