Alternatives and similar repositories for vhdl-ext

Users that are interested in vhdl-ext are comparing it to the libraries listed below

• gmlarumbe / verilog-ext
  Verilog Extensions for Emacs
  ☆61Updated last month
• embed-me / vunit-mode
  A simple Emacs minor mode for VUnit
  ☆12Updated last year
• gmlarumbe / verilog-ts-mode
  Emacs Verilog Tree-sitter Major-mode
  ☆12Updated last month
• gmlarumbe / fpga
  fpga.el - FPGA & ASIC Utils for Emacs
  ☆22Updated last month
• veripool / verilog-mode
  Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
  ☆271Updated 3 months ago
• jwwebbopen / VerilogTools
  Tools for Verilog HDL development.
  ☆10Updated 12 years ago
• ghdl / ghdl-language-server
  Language server based on ghdl
  ☆91Updated last month
• alemuller / tree-sitter-vhdl
  VHDL grammar for tree-sitter
  ☆31Updated last year
• suoto / hdl_checker
  Repurposing existing HDL tools to help writing better code
  ☆207Updated 11 months ago
• imc-trading / svlangserver
  ☆109Updated 11 months ago
• dallingham / verilog-mode-snippets
  A set of yasnippets for emacs that assist with SystemVerilog
  ☆11Updated 13 years ago
• OSVVM / Documentation
  OSVVM Documentation
  ☆33Updated last week
• jwwebbopen / SystemVerilogTools
  Tools for SystemVerilog development.
  ☆15Updated 7 years ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆39Updated 3 months ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆64Updated 2 weeks ago
• alexforencich / cocotbext-i2c
  I2C models for cocotb
  ☆34Updated last month
• Lenty / SLiCAP_python
  Open-source version of SLiCAP, implemented in python
  ☆36Updated 5 months ago
• CESNET / ofm
  Open FPGA Modules
  ☆23Updated 7 months ago
• TripRichert / viv-prj-gen
  tcl scripts used to build or generate vivado projects automatically
  ☆31Updated last year
• g2384 / VHDLFormatter
  VHDL formatter web online written in typescript
  ☆55Updated 2 years ago
• PyFPGA / HDLconv
  HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-sla…
  ☆24Updated 2 months ago
• hVHDL / hVHDL_example_project
  An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…
  ☆27Updated 4 months ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 3 months ago
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆53Updated 7 months ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆163Updated this week
• HDLUtils / hdlregression
  HDLRegression: Simple, efficient, Python3-based FPGA regression test runner. Streamline the verification workflow.
  ☆24Updated last month
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆58Updated 3 months ago
• gmlarumbe / tree-sitter-systemverilog
  Rewrite of tree-sitter-verilog
  ☆22Updated last month
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆45Updated last year
• wyvernSemi / vproc
  Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
  ☆57Updated 2 months ago