Alternatives and similar repositories for vhdl-ext

Users that are interested in vhdl-ext are comparing it to the libraries listed below

• gmlarumbe / verilog-ext
  Verilog Extensions for Emacs
  ☆61Updated 2 weeks ago
• embed-me / vunit-mode
  A simple Emacs minor mode for VUnit
  ☆12Updated 2 months ago
• gmlarumbe / verilog-ts-mode
  Emacs Verilog Tree-sitter Major-mode
  ☆12Updated 2 weeks ago
• gmlarumbe / fpga
  fpga.el - FPGA & ASIC Utils for Emacs
  ☆22Updated last month
• veripool / verilog-mode
  Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
  ☆272Updated last month
• ghdl / ghdl-language-server
  Language server based on ghdl
  ☆97Updated 4 months ago
• suoto / hdl_checker
  Repurposing existing HDL tools to help writing better code
  ☆217Updated last year
• dallingham / verilog-mode-snippets
  A set of yasnippets for emacs that assist with SystemVerilog
  ☆11Updated 13 years ago
• jwwebbopen / SystemVerilogTools
  Tools for SystemVerilog development.
  ☆15Updated 7 years ago
• Lenty / SLiCAP_python
  Open-source version of SLiCAP, implemented in python
  ☆36Updated 9 months ago
• imc-trading / svlangserver
  ☆119Updated last year
• alemuller / tree-sitter-vhdl
  VHDL grammar for tree-sitter
  ☆31Updated last year
• Remillard / VHDL-Mode
  A package for Sublime Text that aids coding in the VHDL language.
  ☆42Updated 2 years ago
• csantosb / vhdl-tools
  Easier navigation of VHDL sources
  ☆12Updated 5 years ago
• HDLUtils / hdlregression
  HDLRegression: Simple, efficient, Python3-based FPGA regression test runner. Streamline the verification workflow.
  ☆25Updated last week
• jeremiah-c-leary / vhdl-style-guide
  Style guide enforcement for VHDL
  ☆219Updated this week
• VHDL / PoC
  IP Core Library - Published and maintained by the Open Source VHDL Group
  ☆24Updated this week
• jwwebbopen / VerilogTools
  Tools for Verilog HDL development.
  ☆10Updated 13 years ago
• PyFPGA / HDLconv
  HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-sla…
  ☆25Updated 6 months ago
• g2384 / VHDLFormatter
  VHDL formatter web online written in typescript
  ☆57Updated 2 years ago
• wavedrom / cli
  CLI for WaveDrom
  ☆62Updated last year
• tsfpga / tsfpga
  A flexible and scalable development platform for modern FPGA projects.
  ☆32Updated last week
• johonkanen / tube_amplifier_power_supply
  A tube guitar amplifier power supply VHDL project
  ☆17Updated 10 months ago
• fuad1502 / oombak
  Oombak 🌊 is an interactive SystemVerilog simulator UI that runs on your terminal!
  ☆42Updated 3 weeks ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆73Updated this week
• OSVVM / Documentation
  OSVVM Documentation
  ☆35Updated last month
• OSVVM / OSVVM
  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
  ☆248Updated last month
• alexforencich / cocotbext-i2c
  I2C models for cocotb
  ☆36Updated last week
• vhdl-linter / vhdl-linter
  ☆30Updated last year
• miree / gvi
  GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.
  ☆14Updated 5 months ago