Verilog SPI master and slave
☆63Jan 4, 2016Updated 10 years ago
Alternatives and similar repositories for Nitro-Parts-lib-SPI
Users that are interested in Nitro-Parts-lib-SPI are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆14Mar 4, 2025Updated last year
- SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs☆21Dec 15, 2019Updated 6 years ago
- SPI Slave for FPGA in Verilog and VHDL☆234May 11, 2024Updated 2 years ago
- A SPI Master IP written in verilog which is then used to output characters entered on a keypad to a serial LCD screen☆20Dec 5, 2014Updated 11 years ago
- SPI Master for FPGA - VHDL and Verilog☆352Aug 22, 2023Updated 3 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- I2C controller core from Opencores.org☆29Oct 5, 2011Updated 15 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆89Dec 7, 2020Updated 5 years ago
- Unified Verification Environment☆17Jan 17, 2017Updated 9 years ago
- Interface Protocol in Verilog☆52Aug 2, 2019Updated 7 years ago
- UART To SPI☆18Jul 17, 2014Updated 12 years ago
- SPI Master and Slave components to be used in all of FPGAs, written in VHDL.☆47Apr 17, 2020Updated 6 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 11 years ago
- this repository is a project about iic master, created by gyj in second half of 2017☆18Jun 30, 2018Updated 8 years ago
- Verilog network module. Models network traffic from pcap to AXI-Stream☆24Apr 24, 2021Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆72May 8, 2020Updated 6 years ago
- Open source implementation of a x86 processor http://zet.aluzina.org☆11Mar 17, 2014Updated 12 years ago
- SPI master and SPI slave for FPGA written in VHDL☆188Apr 24, 2021Updated 5 years ago
- SPI core☆15Oct 25, 2019Updated 7 years ago
- Trying to learn Wishbone by implementing few master/slave devices☆13Jan 7, 2019Updated 7 years ago
- SHA-256 IP core for ZedBoard (Zynq SoC)☆31Jun 22, 2018Updated 8 years ago
- Various HDL (Verilog) IP Cores☆941Jul 1, 2021Updated 5 years ago
- verilog modules☆17May 4, 2020Updated 6 years ago
- ☆11Dec 18, 2017Updated 8 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- 在FPGA上实现SRIO收发控制器☆11Sep 30, 2022Updated 4 years ago
- This is a practice of verilog coding☆33Oct 19, 2026Updated 2 weeks ago
- Verilog module for calculation of FFT.☆199Aug 22, 2012Updated 14 years ago
- Verilog I2C interface for FPGA implementation☆731Feb 27, 2025Updated last year
- Design and Verification of a Complete Application Specific Integrated Circuit☆12Nov 21, 2016Updated 9 years ago
- An FPGA in your USB Port☆11Jul 1, 2021Updated 5 years ago
- EEZ BB3+ MCU in CM5 form factor☆16Sep 18, 2026Updated last month
- This repo will contain and gather libs and symbols working with LTSpiceIV. Directory structure will be tha same as lib dir in LTSpice to …☆12Apr 2, 2016Updated 10 years ago
- Sound synthetizer with an fpga☆11Mar 14, 2015Updated 11 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- A collection of debugging busses developed and presented at zipcpu.com☆45Jan 18, 2024Updated 2 years ago
- I2C Master and Slave☆42Jul 15, 2015Updated 11 years ago
- Documenting the Xilinx 7-series bit-stream format.☆16Updated this week
- Project related to Cypress FX3 USB 3.0 Controller published on☆17Dec 2, 2019Updated 6 years ago
- A simple SystemVerilog digital phase-locked loop based (roughly) on TI's SDLA005B application note. The design includes a SystemVerilog t…☆16Aug 29, 2022Updated 4 years ago
- 4096bit RSA project, with verilog code, python test code, etc☆47Oct 8, 2019Updated 7 years ago
- Single Port RAM, Dual Port RAM, FIFO☆34May 17, 2022Updated 4 years ago