dirjud / Nitro-Parts-lib-SPILinks
Verilog SPI master and slave
☆62Updated 10 years ago
Alternatives and similar repositories for Nitro-Parts-lib-SPI
Users that are interested in Nitro-Parts-lib-SPI are comparing it to the libraries listed below
Sorting:
- UART -> AXI Bridge☆69Updated 4 years ago
- SDRAM controller with AXI4 interface☆100Updated 6 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68Updated 5 years ago
- DDR2 memory controller written in Verilog☆79Updated 13 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆97Updated 3 years ago
- Interface Protocol in Verilog☆51Updated 6 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆82Updated 3 years ago
- Ethernet MAC 10/100 Mbps☆83Updated 6 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆75Updated 5 years ago
- USB 2.0 Device IP Core☆74Updated 8 years ago
- SPI Slave for FPGA in Verilog and VHDL☆220Updated last year
- Fully parametrizable combinatorial parallel LFSR/CRC module☆160Updated 11 months ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆79Updated 3 years ago
- I2C controller core☆48Updated 3 years ago
- An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器☆89Updated last year
- WISHBONE SD Card Controller IP Core☆130Updated 3 years ago
- Verilog UART☆191Updated 12 years ago
- Small (Q)SPI flash memory programmer in Verilog☆68Updated 3 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆22Updated 6 years ago
- SPI-Flash XIP Interface (Verilog)☆48Updated 4 years ago
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆78Updated 4 years ago
- AXI4 and AXI4-Lite interface definitions☆101Updated 5 years ago
- AHB3-Lite Interconnect☆109Updated last year
- 100 MB/s Ethernet MAC Layer Switch☆15Updated 11 years ago
- A simple implementation of a UART modem in Verilog.☆172Updated 4 years ago
- RTL Verilog library for various DSP modules☆94Updated 3 years ago
- Verilog module to transmit/receive to/from RGMII compatible ethernet PHY☆30Updated 3 years ago
- ☆38Updated 10 years ago
- Basic USB-CDC device core (Verilog)☆85Updated 4 years ago
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆132Updated 5 years ago