Verilog SPI master and slave
☆63Jan 4, 2016Updated 10 years ago
Alternatives and similar repositories for Nitro-Parts-lib-SPI
Users that are interested in Nitro-Parts-lib-SPI are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs☆21Dec 15, 2019Updated 6 years ago
- SPI Slave for FPGA in Verilog and VHDL☆231May 11, 2024Updated 2 years ago
- A SPI Master IP written in verilog which is then used to output characters entered on a keypad to a serial LCD screen☆20Dec 5, 2014Updated 11 years ago
- SPI Master for FPGA - VHDL and Verilog☆341Aug 22, 2023Updated 2 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆80Dec 7, 2020Updated 5 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- UART To SPI☆19Jul 17, 2014Updated 11 years ago
- ☆20Nov 18, 2022Updated 3 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- Verilog network module. Models network traffic from pcap to AXI-Stream☆24Apr 24, 2021Updated 5 years ago
- Unified Verification Environment☆17Jan 17, 2017Updated 9 years ago
- Interface Protocol in Verilog☆52Aug 2, 2019Updated 6 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68May 8, 2020Updated 6 years ago
- Trying to learn Wishbone by implementing few master/slave devices☆13Jan 7, 2019Updated 7 years ago
- SPI master and SPI slave for FPGA written in VHDL☆183Apr 24, 2021Updated 5 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Super scalar Processor design☆21Sep 7, 2014Updated 11 years ago
- SPI core☆14Oct 25, 2019Updated 6 years ago
- 在FPGA上实现SRIO收发控制器☆11Sep 30, 2022Updated 3 years ago
- verilog modules☆15May 4, 2020Updated 6 years ago
- SHA-256 IP core for ZedBoard (Zynq SoC)☆31Jun 22, 2018Updated 7 years ago
- This is a practice of verilog coding☆32Jul 10, 2019Updated 6 years ago
- SPI通信实现FLASH读写