WangXuan95 / FPGA-HDMI
An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器
☆49Updated 8 months ago
Alternatives and similar repositories for FPGA-HDMI:
Users that are interested in FPGA-HDMI are comparing it to the libraries listed below
- An FPGA-based QOI image compressor and decompressor in Verilog. 基于FPGA的QOI图像压缩器和解压器。☆22Updated 6 months ago
- SPI-Flash XIP Interface (Verilog)☆36Updated 3 years ago
- An FPGA-based LZMA compressor for generic data compression. 基于FPGA的LZMA压缩器,用于通用数据压缩。☆79Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 4 years ago
- 【例程】国产高云FPGA 开发板及其工程☆25Updated 5 months ago
- FPGA和USB3.0桥片实现USB3.0通信☆62Updated 3 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆34Updated 4 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆31Updated 4 years ago
- SDRAM controller with AXI4 interface☆89Updated 5 years ago
- An FPGA-based MPEG2 encoder for video compression (1920x1080 120fps). 基于FPGA的MPEG2视频编码器,可实现视频压缩。☆120Updated last year
- A SATA host (HBA) core based on Xilinx FPGA with GTH to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器,用来读写硬盘。☆95Updated last year
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.☆16Updated 5 years ago
- Must-have verilog systemverilog modules☆31Updated 2 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆42Updated last year
- An implementation of JPEG-LS extension (ITU-T T.870).☆32Updated 5 months ago
- FPGA Technology Exchange Group相关文件管理☆43Updated last year
- ☆56Updated 2 years ago
- An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …☆112Updated last year
- Interface Protocol in Verilog☆49Updated 5 years ago
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆68Updated 3 years ago
- Verilog implementation of SHA1/SHA224/SHA256/SHA384/SHA512. 使用Verilog实现的SHA1/SHA224/SHA256/SHA384/SHA512计算器。☆67Updated last year
- IP operations in verilog (simulation and implementation on ice40)☆55Updated 5 years ago
- UART -> AXI Bridge☆60Updated 3 years ago
- Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核☆22Updated 2 years ago
- configurable cordic core in verilog☆48Updated 10 years ago
- An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器,为低端FPGA嵌入式系统提供廉价、大容量的存储。☆168Updated last year
- Gowin DDR3 Controller with AXI4 Implementation | 高云DDR3内存控制器AXI4接口实现☆22Updated last year
- A set of Wishbone Controlled SPI Flash Controllers☆79Updated 2 years ago
- USB 1.1 Host and Function IP core☆21Updated 10 years ago