🔴 SystemVerilog FPGA cores to communicate with FTDI Synchronous/Asynchronous FIFOs (FT245 protocol)
☆47Jul 16, 2021Updated 4 years ago
Alternatives and similar repositories for proto245
Users that are interested in proto245 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge☆35Jun 5, 2021Updated 5 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆101Jun 6, 2020Updated 6 years ago
- An FPGA-based FT232H/FT600 chip controller for rapid data transmission via USB. 使用FT232H/FT600芯片进行FPGA与电脑之间的高速数据传输。☆354May 21, 2024Updated 2 years ago
- Verilog module to communicate with the FT245 interface of an FTDI FT2232H☆17Nov 14, 2020Updated 5 years ago
- VHDL package to provide C-like string formatting☆15May 6, 2022Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆15Apr 11, 2019Updated 7 years ago
- A simple 6502 system built on a Lattice Ultra Plus 5k FPGA☆15Mar 11, 2019Updated 7 years ago
- Updated FPGA source code and binaries for UHD B220 Clone with XC7A200T+AD9361☆49Jun 8, 2025Updated last year
- ☆19Oct 5, 2020Updated 5 years ago
- An implementation of the Sodor 1-Stage RISC-V processor in SpinalHDL.☆14Jun 5, 2019Updated 7 years ago
- Generates simple AXI4-lite IP for use in Vivado from register specifications☆16Apr 11, 2025Updated last year
- converts catgirls to gds files☆15May 24, 2021Updated 5 years ago
- An FPGA-based QOI image compressor and decompressor in Verilog. 基于FPGA的QOI图像压缩器和解压器。☆41Sep 18, 2024Updated last year
- Tiny VGA Pmod board designed in KiCad☆24Sep 4, 2024Updated last year
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Simple demo showing how to use the ping pong FIFO☆17May 2, 2016Updated 10 years ago
- Streaming video over USB using FT232H and Cyclone IV FPGA.☆15Feb 26, 2023Updated 3 years ago
- A first approach of getting a pure Ada program running on an FPGA with SaxonSOC☆10Apr 12, 2021Updated 5 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Feb 17, 2026Updated 4 months ago
- Standalone SDR experiment using multicore MCU☆11Apr 12, 2018Updated 8 years ago
- A min-sum LDPC decoder written in SystemVerilog (IEEE 1800-2012)☆13Jan 8, 2021Updated 5 years ago
- ☆17Oct 6, 2023Updated 2 years ago
- Chisel Examples for the iCESugar FPGA Board☆12May 4, 2021Updated 5 years ago
- Building a simple oscilloscope using FPGA board and PCB.☆22Dec 30, 2020Updated 5 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆22Sep 26, 2025Updated 9 months ago
- KeePass password database import/export library.☆14Nov 21, 2021Updated 4 years ago
- Remora firmware for RP2040 with W5500 Ethernet☆16Jul 21, 2024Updated last year
- This is the fully-functional GNU Radio software-defined radio (SDR) implementation of a LoRa transceiver with all the necessary transceiv…☆22May 30, 2022Updated 4 years ago
- Unnofficial mirror of http://reveng.sourceforge.net/☆29Feb 11, 2017Updated 9 years ago
- Python Utilities to use Xilinx Vivado Tools from Python Scripts☆22Oct 18, 2020Updated 5 years ago
- RMII Firewall FPGA☆25Dec 2, 2019Updated 6 years ago
- Buildroot config for EBAZ4205☆19Feb 18, 2021Updated 5 years ago
- Wishbone controlled I2C controllers☆57Jun 24, 2026Updated 2 weeks ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- AXI4 with a FIFO integrated with VIP☆25Feb 29, 2024Updated 2 years ago
- Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection,…☆17Apr 12, 2020Updated 6 years ago
- FPGA development platform for high-performance RF and digital design☆32Dec 3, 2015Updated 10 years ago
- Verilog models for the GAL22V10 and select PAL devices.☆17Dec 24, 2025Updated 6 months ago
- ☆46May 8, 2020Updated 6 years ago
- A complete 65C02 computer with VGA output on a Lattice Ultra Plus FPGA☆29Jun 12, 2019Updated 7 years ago
- Docker Development Environment for SpinalHDL☆20Aug 8, 2024Updated last year