Alternatives and similar repositories for firtool-standalone-plugin:

Users that are interested in firtool-standalone-plugin are comparing it to the libraries listed below

• j-marjanovic / chisel-bfm-tester
  BFM Tester for Chisel HDL
  ☆14Updated 3 years ago
• mikeurbach / egg-netlist-synthesizer
  Using e-graphs to synthesize netlists from boolean logic.
  ☆14Updated last year
• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆18Updated this week
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆34Updated last year
• TsaiAnson / verif
  ☆11Updated 3 years ago
• dalance / svls-vscode
  SystemVerilog language server client for Visual Studio Code
  ☆20Updated 2 years ago
• pezy-computing / pzbcm
  Basic Common Modules
  ☆36Updated last month
• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆26Updated 2 months ago
• ucb-bar / barstools
  Useful utilities for BAR projects
  ☆30Updated last year
• chipsalliance / diplomacy
  ☆18Updated 6 months ago
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆20Updated 2 years ago
• ucb-bar / chisel-awl
  ☆13Updated 3 years ago
• Dinistro / circt-stream
  A stream to RTL compiler based on MLIR and CIRCT
  ☆15Updated 2 years ago
• abs-tudelft / Tydi-Chisel
  ☆17Updated 3 months ago
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆44Updated last year
• Lampro-Mellon / Quasar
  Quasar 2.0: Chisel equivalent of SweRV-EL2
  ☆28Updated 3 years ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆35Updated 3 years ago
• rameloni / tywaves-chisel
  A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…
  ☆30Updated 2 months ago
• iscas-tis / CHA
  ☆16Updated 6 months ago
• chipsalliance / espresso
  ☆37Updated 11 months ago
• chipsalliance / rocket-chip-inclusive-cache
  An RTL generator for a last-level shared inclusive TileLink cache controller
  ☆15Updated 5 months ago
• sifive / block-pio-sifive
  An example of on-boarding a PIO block in with duh and wake
  ☆12Updated 4 years ago
• sequencer / zaozi
  The experimental work to rewrite Chisel in pure Scala 3 and the Panama Project
  ☆19Updated last week
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆29Updated 2 months ago
• freechipsproject / chisel-coverage
  A coverage library for Chisel designs
  ☆11Updated 4 years ago
• nhynes / chisel3-axi
  Chisel3 AXI4-{Lite, Full, Stream} Definitions
  ☆14Updated 6 years ago
• freechipsproject / www.chisel-lang.org
  The home of the Chisel3 website
  ☆20Updated 7 months ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆38Updated last month
• chipsalliance / fpga-interchange-schema
  ☆52Updated 2 years ago
• ucb-bar / chisel-gui
  A prototype GUI for chisel-development
  ☆52Updated 4 years ago