Alternatives and similar repositories for zaozi

Users that are interested in zaozi are comparing it to the libraries listed below

• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆31Updated 3 months ago
• chipsalliance / diplomacy
  ☆21Updated 8 months ago
• chipsalliance / playground
  chipyard in mill :P
  ☆77Updated 2 years ago
• ucb-bar / chisel-gui
  A prototype GUI for chisel-development
  ☆51Updated 5 years ago
• chipsalliance / chisel-nix
  Nix template for the chisel-based industrial designing flows.
  ☆49Updated 7 months ago
• chipsalliance / espresso
  ☆41Updated 5 months ago
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆50Updated last week
• chipsalliance / rvdecoderdb
  The Scala parser to parse riscv/riscv-opcodes generate
  ☆21Updated 2 months ago
• rameloni / tywaves-chisel
  A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…
  ☆51Updated last year
• pku-liang / ksim
  ☆49Updated 10 months ago
• iscas-tis / ChiRVFormal
  Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.
  ☆15Updated 5 months ago
• arch-simulator-sig / chisel-env
  Basic chisel difftest environment for RTL design (WIP
  ☆19Updated 8 months ago
• iscas-tis / chisel-formal-verification
  Formal verification tools for Chisel and RISC-V
  ☆13Updated last year
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆51Updated last week
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆188Updated 6 months ago
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• NovyWave / NovyWave
  Modern GTKWave alternative
  ☆24Updated 3 weeks ago
• euphoric-hardware / rtl-simulation-reading
  ☆18Updated last week
• ucsc-vama / essent
  high-performance RTL simulator
  ☆182Updated last year
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆36Updated last month
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆110Updated last week
• chipsalliance / rocket-chip-inclusive-cache
  An RTL generator for a last-level shared inclusive TileLink cache controller
  ☆22Updated 10 months ago
• DFiantHDL / DFHDL
  DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language
  ☆92Updated this week
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆21Updated 8 months ago
• sequencer / arithmetic
  ☆33Updated 8 months ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆117Updated 3 years ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆91Updated 2 weeks ago
• nhynes / chisel3-axi
  Chisel3 AXI4-{Lite, Full, Stream} Definitions
  ☆15Updated 6 years ago
• abs-tudelft / Tydi-Chisel
  ☆18Updated last month
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆86Updated last year