Alternatives and similar repositories for zaozi

Users that are interested in zaozi are comparing it to the libraries listed below

• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆30Updated 3 weeks ago
• chipsalliance / diplomacy
  ☆21Updated 6 months ago
• chipsalliance / playground
  chipyard in mill :P
  ☆78Updated last year
• chipsalliance / rocket-chip-inclusive-cache
  An RTL generator for a last-level shared inclusive TileLink cache controller
  ☆22Updated 8 months ago
• iscas-tis / chisel-formal-verification
  Formal verification tools for Chisel and RISC-V
  ☆13Updated last year
• chipsalliance / chisel-nix
  Nix template for the chisel-based industrial designing flows.
  ☆45Updated 4 months ago
• ucb-bar / chisel-gui
  A prototype GUI for chisel-development
  ☆52Updated 5 years ago
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆48Updated last week
• chipsalliance / rvdecoderdb
  The Scala parser to parse riscv/riscv-opcodes generate
  ☆21Updated 2 weeks ago
• iscas-tis / ChiRVFormal
  Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.
  ☆14Updated 3 months ago
• chipsalliance / espresso
  ☆40Updated 3 months ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆35Updated 4 months ago
• sequencer / arithmetic
  ☆33Updated 5 months ago
• arch-simulator-sig / chisel-env
  Basic chisel difftest environment for RTL design (WIP
  ☆18Updated 6 months ago
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• pku-liang / ksim
  ☆46Updated 8 months ago
• rameloni / tywaves-chisel
  A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…
  ☆49Updated 10 months ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆88Updated last week
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆183Updated 4 months ago
• OpenXiangShan / gsim
  ☆53Updated 2 weeks ago
• OpenXiangShan / YunSuan
  This repo includes XiangShan's function units
  ☆27Updated this week
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆62Updated 3 years ago
• DFiantHDL / DFHDL
  DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language
  ☆88Updated this week
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆84Updated last year
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆33Updated last year
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆116Updated 3 years ago
• abs-tudelft / Tydi-Chisel
  ☆18Updated 5 months ago
• ucsc-vama / essent
  high-performance RTL simulator
  ☆175Updated last year
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆105Updated 3 months ago
• OpenXiangShan / Deterload
  Xiangshan deterministic workloads generator
  ☆20Updated 4 months ago