Alternatives and similar repositories for riscv-CMOs

Users that are interested in riscv-CMOs are comparing it to the libraries listed below

• riscv / riscv-aia
  ☆92Updated this week
• riscvarchive / riscv-aclint
  ☆42Updated 3 years ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆69Updated last year
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆229Updated 8 months ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆125Updated this week
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆178Updated 2 months ago
• riscv-ovpsim / imperas-riscv-tests
  ☆182Updated last year
• riscv / riscv-test-env
  ☆49Updated 2 months ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆105Updated last week
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆101Updated this week
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆155Updated 3 years ago
• riscvarchive / riscv-code-size-reduction
  ☆149Updated last year
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆159Updated 5 years ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆113Updated this week
• riscv-non-isa / tg-nexus-trace
  RISC-V Nexus Trace TG documentation and reference code
  ☆51Updated 7 months ago
• riscvarchive / riscv-eabi-spec
  Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.
  ☆27Updated 4 years ago
• ucb-bar / libgloss-htif
  A libgloss replacement for RISC-V that supports HTIF
  ☆38Updated last year
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆171Updated 2 weeks ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆117Updated 3 weeks ago
• riscv / riscv-profiles
  RISC-V Architecture Profiles
  ☆160Updated 5 months ago
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆82Updated 2 months ago
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆48Updated last week
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆71Updated last month
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆195Updated last year
• carrv / carrv.github.io
  Workshop on Computer Architecture Research with RISC-V (CARRV)
  ☆39Updated 8 months ago
• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆42Updated 6 months ago
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆191Updated this week
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆89Updated 2 weeks ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆80Updated 4 months ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆147Updated 9 months ago