SamuelBayliss / PotholesLinks
Polyhedral Compilation tool for High Level Synthesis.
☆10Updated 11 years ago
Alternatives and similar repositories for Potholes
Users that are interested in Potholes are comparing it to the libraries listed below
Sorting:
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 7 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 10 months ago
- Convert C files into Verilog☆17Updated 6 years ago
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 3 years ago
- SForum 2020 : "A Run-time Hardware Routing Implementation for CGRA Overlays" code and data.☆11Updated 4 years ago
- An LLVM pass to prove that an II works for the given loop for Vitis HLS☆11Updated 3 years ago
- The PE for the second generation CGRA (garnet).☆17Updated 2 months ago
- ☆27Updated 7 years ago
- The Shang high-level synthesis framework☆120Updated 11 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated 3 weeks ago
- Collection of test cases for Yosys☆18Updated 3 years ago
- netlistDB - Intermediate format for digital hardware representation with graph database API☆31Updated 4 years ago
- C++ parsing library for simple formats used in logic synthesis and formal verification☆36Updated last year
- C++17 implementation of an AST for Verilog code generation☆24Updated 2 years ago
- The ANUBIS benchmark suite for Incremental Synthesis☆12Updated 4 years ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- ☆26Updated 2 years ago
- Chisel library for Unum Type-III Posit Arithmetic☆39Updated 3 months ago
- RTLCheck☆22Updated 6 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆13Updated 8 years ago
- Gate-Level Simulation on a GPU☆10Updated 8 years ago
- DATuner Repository☆18Updated 6 years ago
- Rapid system integration of high-level synthesis kernels using the LEAP FPGA framework☆12Updated 9 years ago
- Polyhedral High-Level Synthesis in MLIR☆33Updated 2 years ago
- ☆24Updated 4 years ago
- REAPR (Reconfigurable Engine for Automata Processing) is a general-purpose framework for accelerating automata processing applications su…☆16Updated 6 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 3 years ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆16Updated 5 years ago
- An advanced header-only exact synthesis library☆27Updated 2 years ago