SamuelBayliss / Potholes

Related projects ⓘ

Alternatives and complementary repositories for Potholes

• Junyi-Liu / benchmarks-HLS
  Benchmarks, testbenches, and transformed codes for high-level synthesis research
  ☆13Updated 7 years ago
• HardwareIR / netlistDB
  netlistDB - Intermediate format for digital hardware representation with graph database API
  ☆29Updated 3 years ago
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆16Updated 2 months ago
• cucapra / latte21
  Languages, Tools, and Techniques for Accelerator Design
  ☆33Updated 3 years ago
• jianyicheng / iiProver
  An LLVM pass to prove that an II works for the given loop for Vitis HLS
  ☆11Updated 3 years ago
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆19Updated 2 years ago
• lesc-ufv / cgra-routing
  SForum 2020 : "A Run-time Hardware Routing Implementation for CGRA Overlays" code and data.
  ☆11Updated 4 years ago
• Blaok / tapa
  TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…
  ☆19Updated 2 months ago
• spcl / apfp
  FPGA acceleration of arbitrary precision floating point computations.
  ☆37Updated 2 years ago
• David-Durst / embeddedHaskellAetherling
  ☆25Updated 2 years ago
• SiliconSemantics / firrtlator
  firrtlator is a FIRRTL C++ library
  ☆21Updated 7 years ago
• UCSBarchlab / Charm
  A Language for Closed-form High-level ARchitecture Modeling
  ☆18Updated 4 years ago
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated last year
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated last year
• leonardt / verilogAST-cpp
  C++17 implementation of an AST for Verilog code generation
  ☆24Updated last year
• dillonhuff / clockwork
  A polyhedral compiler for hardware accelerators
  ☆56Updated 3 months ago
• wincle626 / HLS_Legup
  ☆26Updated 7 years ago
• RohanNagar / parallel-logic-networks
  Gate-Level Simulation on a GPU
  ☆9Updated 7 years ago
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆16Updated 2 years ago
• PacoReinaCampo / SoC-RISCV
  System on Chip with RISCV-32 / RISCV-64 / RISCV-128
  ☆20Updated last week
• kumasento / polsca
  Polyhedral High-Level Synthesis in MLIR
  ☆29Updated last year
• xprova / netlist-graph
  Java library for parsing and manipulating graph representations of gate-level Verilog netlists
  ☆13Updated 7 years ago
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆18Updated this week
• whaaswijk / percy
  An advanced header-only exact synthesis library
  ☆23Updated last year
• sfu-arch / muir
  ☆22Updated 4 years ago
• ted-xie / REAPR
  REAPR (Reconfigurable Engine for Automata Processing) is a general-purpose framework for accelerating automata processing applications su…
  ☆15Updated 5 years ago
• paripath / cdf
  Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format
  ☆12Updated 4 years ago
• VP-Vibes / VPV-Peripherals
  Library of example SystemC/TLM peripherals for various SoCs based on the SCS library
  ☆12Updated last month
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆61Updated 4 years ago