SamuelBayliss / Potholes
Polyhedral Compilation tool for High Level Synthesis.
☆10Updated 10 years ago
Alternatives and similar repositories for Potholes:
Users that are interested in Potholes are comparing it to the libraries listed below
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 7 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 4 months ago
- netlistDB - Intermediate format for digital hardware representation with graph database API☆30Updated 3 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆20Updated this week
- The PE for the second generation CGRA (garnet).☆17Updated 4 months ago
- SForum 2020 : "A Run-time Hardware Routing Implementation for CGRA Overlays" code and data.☆11Updated 4 years ago
- Convert C files into Verilog☆16Updated 5 years ago
- ☆25Updated 2 years ago
- FPGA acceleration of arbitrary precision floating point computations.☆38Updated 2 years ago
- An LLVM pass to prove that an II works for the given loop for Vitis HLS☆11Updated 3 years ago
- Collection of test cases for Yosys☆18Updated 3 years ago
- ☆26Updated 7 years ago
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 3 years ago
- A polyhedral compiler for hardware accelerators☆55Updated 5 months ago
- Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…☆56Updated 4 years ago
- Benchmarks for Yosys development☆23Updated 4 years ago
- Welcome to Birds-of-a-Feather: Open-Source-Academic-EDA-Software !☆12Updated 5 years ago
- firrtlator is a FIRRTL C++ library☆21Updated 8 years ago
- REAPR (Reconfigurable Engine for Automata Processing) is a general-purpose framework for accelerating automata processing applications su…☆16Updated 5 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated last year
- Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format☆12Updated 4 years ago
- Rapid system integration of high-level synthesis kernels using the LEAP FPGA framework☆12Updated 8 years ago
- OpenDesign Flow Database☆16Updated 6 years ago
- Polyhedral High-Level Synthesis in MLIR☆29Updated last year
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 2 years ago
- An advanced header-only exact synthesis library☆24Updated 2 years ago
- Streaming Message Interface: High-Performance Distributed Memory Programming on Reconfigurable Hardware☆16Updated 2 years ago
- DATuner Repository☆18Updated 6 years ago
- C++ parsing library for simple formats used in logic synthesis and formal verification☆35Updated 6 months ago
- ☆13Updated 4 years ago