Featherweight-IP / fwriscLinks
Featherweight RISC-V implementation
☆53Updated 3 years ago
Alternatives and similar repositories for fwrisc
Users that are interested in fwrisc are comparing it to the libraries listed below
Sorting:
- SoftCPU/SoC engine-V☆54Updated 6 months ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆65Updated 7 years ago
- Wishbone interconnect utilities☆41Updated 7 months ago
- Yet Another RISC-V Implementation☆97Updated last year
- An Open Source configuration of the Arty platform☆132Updated last year
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆91Updated 7 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆95Updated 5 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆106Updated 3 weeks ago
- Extensible FPGA control platform☆61Updated 2 years ago
- Xilinx Unisim Library in Verilog☆85Updated 5 years ago
- FuseSoC standard core library☆147Updated 4 months ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 9 years ago
- ☆64Updated 6 years ago
- Spen's Official OpenOCD Mirror☆50Updated 6 months ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆80Updated 5 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆54Updated last week
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.☆32Updated 5 years ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆123Updated 9 years ago
- CMod-S6 SoC☆42Updated 7 years ago
- Wishbone to AXI bridge (VHDL)☆42Updated 6 years ago
- Verilog wishbone components☆118Updated last year
- Demo SoC for SiliconCompiler.☆61Updated this week
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆67Updated 3 weeks ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆67Updated this week
- LatticeMico32 soft processor☆107Updated 10 years ago
- Naive Educational RISC V processor☆88Updated 2 months ago