lcbcFoo / ReonV
ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 architecture, now changed to RISC-V ISA.
☆71Updated last year
Related projects: ⓘ
- MR1 formally verified RISC-V CPU☆50Updated 5 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆79Updated 5 years ago
- A tiny POWER Open ISA soft processor written in Chisel☆101Updated last year
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 2 years ago
- FuseSoC standard core library☆105Updated last month
- OmniXtend cache coherence protocol☆76Updated 4 years ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆42Updated last year
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆80Updated 3 years ago
- FPGA reference design for the the Swerv EH1 Core☆65Updated 4 years ago
- Firmware infrastructure, contain RTOS Abstraction Layer, demos and more...☆52Updated 2 years ago
- LatticeMico32 soft processor☆102Updated 9 years ago
- Project X-Ray Database: XC7 Series☆63Updated 2 years ago
- SoftCPU/SoC engine-V☆54Updated last year
- An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …☆43Updated 3 weeks ago
- nextpnr portable FPGA place and route tool☆20Updated last month
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 4 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆54Updated this week
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆86Updated 3 years ago
- Experiments with fixed function renderers and Chisel HDL☆56Updated 5 years ago
- Yet Another RISC-V Implementation☆82Updated 8 months ago
- ☆39Updated 4 years ago
- Featherweight RISC-V implementation☆52Updated 2 years ago
- 😎 A curated list of awesome RISC-V implementations☆125Updated last year
- A utility for Composing FPGA designs from Peripherals☆167Updated 8 months ago
- A 32-bit Microcontroller featuring a RISC-V core☆145Updated 6 years ago
- Spen's Official OpenOCD Mirror☆45Updated 6 months ago
- ☆76Updated 6 months ago
- Facilitates building open source tools for working with hardware description languages (HDLs)☆61Updated 4 years ago
- SymbiFlow WIP changes for Yosys Open SYnthesis Suite☆37Updated 6 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆57Updated 5 months ago