lcbcFoo / ReonVLinks
ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 architecture, now changed to RISC-V ISA.
☆79Updated 3 years ago
Alternatives and similar repositories for ReonV
Users that are interested in ReonV are comparing it to the libraries listed below
Sorting:
- Basic RISC-V CPU implementation in VHDL.☆172Updated 5 years ago
- MR1 formally verified RISC-V CPU☆57Updated 7 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆70Updated last month
- SoftCPU/SoC engine-V☆55Updated 10 months ago
- Project X-Ray Database: XC7 Series☆74Updated 4 years ago
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆65Updated 8 months ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆91Updated 6 years ago
- An Open Source configuration of the Arty platform☆131Updated 2 years ago
- LatticeMico32 soft processor☆107Updated 11 years ago
- A 32-bit Microcontroller featuring a RISC-V core☆160Updated 7 years ago
- CoreScore☆172Updated 2 months ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆72Updated 7 years ago
- A tiny POWER Open ISA soft processor written in Chisel☆114Updated 2 years ago
- Small footprint and configurable Inter-Chip communication cores☆66Updated this week
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆71Updated 3 years ago
- A utility for Composing FPGA designs from Peripherals☆186Updated last year
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆45Updated 3 years ago
- An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …☆50Updated last year
- OpenSPARC-based SoC☆75Updated 11 years ago
- FuseSoC standard core library☆151Updated 2 months ago
- Featherweight RISC-V implementation☆53Updated 4 years ago
- ☆27Updated 11 months ago
- nextpnr portable FPGA place and route tool☆20Updated last year
- YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includ…☆45Updated last year
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆81Updated 6 years ago
- Virtual Development Board☆64Updated 4 years ago
- CMod-S6 SoC☆45Updated 8 years ago
- A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA☆24Updated 2 years ago
- MIPSfpga+ allows loading programs via UART and has a switchable clock☆112Updated 6 years ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆125Updated 9 years ago