lcbcFoo / ReonVLinks
ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 architecture, now changed to RISC-V ISA.
☆77Updated 2 years ago
Alternatives and similar repositories for ReonV
Users that are interested in ReonV are comparing it to the libraries listed below
Sorting:
- MR1 formally verified RISC-V CPU☆53Updated 6 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆88Updated 5 years ago
- OpenSPARC-based SoC☆69Updated 10 years ago
- SoftCPU/SoC engine-V☆54Updated 3 months ago
- Firmware infrastructure, contain RTOS Abstraction Layer, demos and more...☆52Updated 3 years ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆61Updated last month
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …☆46Updated 10 months ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆81Updated 5 years ago
- Basic RISC-V CPU implementation in VHDL.☆167Updated 4 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆65Updated 7 years ago
- A 32-bit Microcontroller featuring a RISC-V core☆153Updated 7 years ago
- A tiny POWER Open ISA soft processor written in Chisel☆109Updated 2 years ago
- Project X-Ray Database: XC7 Series☆70Updated 3 years ago
- Yet Another RISC-V Implementation☆94Updated 9 months ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆146Updated 8 months ago
- LatticeMico32 soft processor☆106Updated 10 years ago
- 😎 A curated list of awesome RISC-V implementations☆137Updated 2 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆65Updated last week
- pulp_soc is the core building component of PULP based SoCs☆80Updated 4 months ago
- Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator☆203Updated 4 years ago
- The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …☆48Updated 2 months ago
- nextpnr portable FPGA place and route tool☆20Updated 10 months ago
- Experiments with fixed function renderers and Chisel HDL☆59Updated 6 years ago
- Parallel Array of Simple Cores. Multicore processor.☆100Updated 6 years ago
- The OpenRISC 1000 architectural simulator☆76Updated 2 months ago
- Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations☆74Updated 2 years ago