EE 260 Winter 2017: Advanced VLSI Design
☆67Dec 13, 2016Updated 9 years ago
Alternatives and similar repositories for ee260_lab
Users that are interested in ee260_lab are comparing it to the libraries listed below
Sorting:
- ☆10Jun 7, 2022Updated 3 years ago
- DTMF Receiver: Logic Synthesis and Physical Design using genus and innovus in 90nm process node☆14Dec 1, 2023Updated 2 years ago
- ☆20Oct 16, 2018Updated 7 years ago
- A light-weight hardware oriented synchronous stream cipher.☆12Mar 19, 2022Updated 3 years ago
- Simulator for a superscalar processor with dynamic scheduling and branch prediction☆15Nov 23, 2018Updated 7 years ago
- Animals classification using CNN☆10Aug 29, 2019Updated 6 years ago
- My personal Electronics projects versioning repo.☆13Dec 9, 2013Updated 12 years ago
- General Purpose IO with APB4 interface☆15May 10, 2024Updated last year
- FPGA Labs for EECS 151/251A (Fall 2021)☆11Oct 20, 2021Updated 4 years ago
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- ☆10Sep 4, 2017Updated 8 years ago
- ☆10Apr 8, 2021Updated 4 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.☆31Aug 28, 2025Updated 6 months ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 3 years ago
- ☆14Feb 2, 2026Updated last month
- Simple PyTorch profiler that combines DeepSpeed Flops Profiler and TorchInfo☆11Feb 12, 2023Updated 3 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆11Jan 27, 2022Updated 4 years ago
- Pipelined 64-bit RISC-V core☆15Mar 7, 2024Updated 2 years ago
- ☆16Jan 18, 2025Updated last year
- HeliosXCore is a Superscalar Out-of-order RISC-V Processor Core.☆10Mar 8, 2024Updated 2 years ago
- ☆11Oct 10, 2019Updated 6 years ago
- Header-only C/C++ static keys to avoid the overhead of conditional branches☆14Feb 10, 2024Updated 2 years ago
- Contains the code for the Flexus cycle-accurate simulator, used in QFlex.☆14Feb 28, 2026Updated last week
- VCD (Value Change Dump) Tracing for C++☆14Mar 1, 2026Updated last week
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆17Sep 2, 2023Updated 2 years ago
- openMSP430 CPU core (from OpenCores)☆22Oct 14, 2022Updated 3 years ago
- RISC-V Nox core☆71Jul 22, 2025Updated 7 months ago
- RTL Design and Verification☆18Jan 4, 2021Updated 5 years ago
- A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.☆16Sep 27, 2022Updated 3 years ago
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆17Jan 30, 2023Updated 3 years ago
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆20Apr 7, 2025Updated 11 months ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆72Dec 29, 2025Updated 2 months ago
- 给NEMU移植Linux Kernel!☆22Jun 1, 2025Updated 9 months ago
- Implementation of Direct-Mapped-Cache to hold 256 blocks, 16 32-bit instruction/Data per block with 32-bit address line☆14Dec 29, 2018Updated 7 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆40Jun 19, 2024Updated last year
- Universal Advanced JTAG Debug Interface☆17May 10, 2024Updated last year
- Basic chisel difftest environment for RTL design (WIP☆20Mar 8, 2025Updated last year
- Firmware for the Cypress EZ-USB FX3 microcontroller on the FreeSRP☆17Apr 15, 2017Updated 8 years ago
- RISC-V soft-core PEs for TaPaSCo☆23Jan 30, 2026Updated last month