EE 260 Winter 2017: Advanced VLSI Design
☆69Dec 13, 2016Updated 9 years ago
Alternatives and similar repositories for ee260_lab
Users that are interested in ee260_lab are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A light-weight hardware oriented synchronous stream cipher.☆12Mar 19, 2022Updated 4 years ago
- Animals classification using CNN☆10Aug 29, 2019Updated 7 years ago
- ☆10Jun 7, 2022Updated 4 years ago
- EE 272B - VLSI Design Project☆15Jun 24, 2021Updated 5 years ago
- Digital IC design and vlsi notes☆15Jun 24, 2020Updated 6 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 4 years ago
- ☆23Oct 16, 2018Updated 7 years ago
- My personal Electronics projects versioning repo.☆13Dec 9, 2013Updated 12 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆21Sep 2, 2023Updated 2 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆11Jan 27, 2022Updated 4 years ago
- ☆10Apr 8, 2021Updated 5 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆22May 12, 2025Updated last year
- RISC-V soft-core PEs for TaPaSCo☆24Jul 24, 2026Updated last month
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- DTMF Receiver: Logic Synthesis and Physical Design using genus and innovus in 90nm process node☆19Dec 1, 2023Updated 2 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.☆37Aug 28, 2025Updated last year
- FPGA250 aboard the eFabless Caravel☆33Dec 22, 2020Updated 5 years ago
- ☆31Oct 3, 2022Updated 3 years ago
- ☆16Jun 28, 2021Updated 5 years ago
- Systolic Array implementation for ASIC Course☆15Nov 26, 2023Updated 2 years ago
- Educational Design Kit for Synopsys Tools with a set of Characterized Standard Cell Library☆38Jan 18, 2022Updated 4 years ago
- GDS visualization, geometry analysis, and parallelized capacitance extraction at field-solver accuracy. MS thesis project.☆26Jul 1, 2024Updated 2 years ago
- Present Crypto Engine in Verilog☆12Feb 27, 2016Updated 10 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Simodense: a RISC-V softcore for custom SIMD instructions☆17Aug 9, 2026Updated 3 weeks ago
- Alpha64 R10000 Two-Way Superscalar Processor☆12May 6, 2019Updated 7 years ago
- openMSP430 CPU core (from OpenCores)☆22Oct 14, 2022Updated 3 years ago
- Universal Advanced JTAG Debug Interface☆17May 10, 2024Updated 2 years ago
- HSPICE and MATLAB simulation files of a tracking SAR ADC☆29Jun 29, 2024Updated 2 years ago
- Implementation of Direct-Mapped-Cache to hold 256 blocks, 16 32-bit instruction/Data per block with 32-bit address line☆15Dec 29, 2018Updated 7 years ago
- RTL + Synthesis + APR☆11Aug 3, 2025Updated last year
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆21Jul 4, 2026Updated last month
- A general framework for optimizing DNN dataflow on systolic array☆40Jan 2, 2021Updated 5 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ☆16Jan 20, 2021Updated 5 years ago
- Courseworks of CS6165 VLSI Physical Design Automation, NTHU.☆49Jan 23, 2021Updated 5 years ago
- General Purpose IO with APB4 interface☆17May 10, 2024Updated 2 years ago
- RTL Design and Verification☆21Jan 4, 2021Updated 5 years ago
- Header-only C/C++ static keys to avoid the overhead of conditional branches☆14Feb 10, 2024Updated 2 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆19May 29, 2018Updated 8 years ago
- A 32 point radix-2 FFT module written in Verilog☆25Jun 28, 2020Updated 6 years ago