sheldonucr / ee260_lab
EE 260 Winter 2017: Advanced VLSI Design
☆57Updated 7 years ago
Related projects: ⓘ
- This is a tutorial on standard digital design flow☆71Updated 3 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆57Updated 3 years ago
- Generic FIFO implementation with optional FWFT☆53Updated 4 years ago
- General Purpose AXI Direct Memory Access☆44Updated 4 months ago
- Introductory course into static timing analysis (STA).☆54Updated 5 months ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆40Updated 4 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆26Updated 4 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆41Updated 5 months ago
- Asynchronous fifo in verilog☆32Updated 8 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆47Updated 7 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆65Updated 5 years ago
- Static Timing Analysis Full Course☆43Updated last year
- A verilog implementation for Network-on-Chip☆60Updated 6 years ago
- AXI4 and AXI4-Lite interface definitions☆82Updated 4 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆26Updated last year
- AHB DMA 32 / 64 bits☆48Updated 10 years ago
- ☆24Updated 5 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆20Updated last year
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆34Updated 2 years ago
- Implementing Different Adder Structures in Verilog☆54Updated 5 years ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆58Updated 2 years ago
- round robin arbiter☆66Updated 10 years ago
- IEEE 754 floating point library in system-verilog and vhdl☆53Updated 3 months ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆51Updated last month
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆37Updated 3 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆33Updated 9 months ago
- Parameterized Booth Multiplier in Verilog 2001☆46Updated last year
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11Updated 3 years ago
- DDR2 memory controller written in Verilog☆72Updated 12 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆79Updated 3 years ago