sheldonucr / ee260_labLinks
EE 260 Winter 2017: Advanced VLSI Design
☆66Updated 8 years ago
Alternatives and similar repositories for ee260_lab
Users that are interested in ee260_lab are comparing it to the libraries listed below
Sorting:
- General Purpose AXI Direct Memory Access☆60Updated last year
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆79Updated 4 years ago
- This is a tutorial on standard digital design flow☆79Updated 4 years ago
- Introductory course into static timing analysis (STA).☆98Updated 3 months ago
- Implementing Different Adder Structures in Verilog☆73Updated 6 years ago
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆50Updated 4 years ago
- Generic FIFO implementation with optional FWFT☆60Updated 5 years ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- ☆37Updated 6 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆36Updated 2 years ago
- SRAM☆22Updated 5 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆12Updated 4 years ago
- BlackParrot on Zynq☆48Updated this week
- SystemVerilog modules and classes commonly used for verification☆50Updated 9 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆72Updated 10 months ago
- ☆29Updated 5 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆67Updated 8 months ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last week
- ☆64Updated 3 years ago
- Two Level Cache Controller implementation in Verilog HDL☆53Updated 5 years ago
- AXI4 and AXI4-Lite interface definitions☆96Updated 5 years ago
- Asynchronous fifo in verilog☆35Updated 9 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆47Updated last year
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆61Updated last year
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆74Updated 4 years ago
- Simple single-port AXI memory interface☆46Updated last year
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆70Updated 4 years ago