Alternatives and similar repositories for HGQ

Users that are interested in HGQ are comparing it to the libraries listed below

• fastmachinelearning / hls4ml-tutorial
  Tutorial notebooks for hls4ml
  ☆348Updated 3 weeks ago
• IMPETUS-UdeS / rule4ml
  Resource Utilization and Latency Estimation for ML on FPGA.
  ☆14Updated this week
• Xilinx / logicnets
  Train and deploy LUT-based neural networks on FPGAs
  ☆97Updated last year
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆85Updated last month
• thesps / conifer
  Fast inference of Boosted Decision Trees in FPGAs
  ☆55Updated last month
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆58Updated 3 years ago
• Xilinx / finn-examples
  Dataflow QNN inference accelerator examples on FPGAs
  ☆222Updated 3 months ago
• awai54st / LUTNet
  ☆58Updated 5 years ago
• adamsolomou / SC-DNN
  Stochastic Computing for Deep Neural Networks
  ☆33Updated 4 years ago
• ECASLab / cynq
  PYNQ bindings for C and C++ to avoid requiring Python or Vitis to execute hardware acceleration.
  ☆26Updated 2 months ago
• KULeuven-MICAS / zigzag
  HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators
  ☆152Updated last week
• robertoBosio / NN2FPGA
  From Pytorch model to C++ for Vitis HLS
  ☆17Updated last week
• MartaAndronic / NeuraLUT
  NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions
  ☆37Updated 3 months ago
• FPGA4HEP / course_material
  ☆34Updated 5 years ago
• MakarenaLabs / Xilinx-FPGA-HLS-PYNQ-ALVEO-Flow
  Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.
  ☆30Updated 5 years ago
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆202Updated this week
• fastmachinelearning / models
  Models and examples built with hls4ml
  ☆12Updated 5 years ago
• MartaAndronic / PolyLUT
  PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…
  ☆54Updated last year
• AlexMontgomerie / fpgaconvnet-hls
  ☆30Updated 8 months ago
• mit-emze / cimloop
  ☆61Updated last month
• AlexMontgomerie / fpgaconvnet-model
  Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.
  ☆29Updated 8 months ago
• ChFrenkel / ReckOn
  ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales - HDL source code and documentation.
  ☆85Updated 3 years ago
• arc-research-lab / CHARM
  CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture
  ☆147Updated this week
• neurosim / NeuroSim
  Central repository for all NeuroSim versions. Each version is uploaded in a separate branch. Updates to the versions will be reflected he…
  ☆59Updated 3 weeks ago
• neurosim / DNN_NeuroSim_V2.0
  Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)
  ☆52Updated 4 years ago
• spcl / hls_tutorial_examples
  Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
  ☆200Updated 3 years ago
• Linger0 / SRAM-Compute-In-Memory
  A collection of research papers on SRAM-based compute-in-memory architectures.
  ☆29Updated last year
• gnodipac886 / ViT-FPGA-TPU
  FPGA based Vision Transformer accelerator (Harvard CS205)
  ☆124Updated 5 months ago
• weierwan / Neurram_48core
  Verilog and Python drivers and APIs for Neurram 48-core chip
  ☆38Updated 3 years ago
• AlexMontgomerie / fpgaconvnet-tutorial
  A collection of tutorials for the fpgaConvNet framework.
  ☆42Updated 9 months ago