MicrochipTech / fpga-hls-examplesLinks
Open-Source HLS Examples for Microchip FPGAs
☆48Updated 3 months ago
Alternatives and similar repositories for fpga-hls-examples
Users that are interested in fpga-hls-examples are comparing it to the libraries listed below
Sorting:
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆91Updated 9 months ago
- PYNQ Composabe Overlays☆73Updated last year
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆72Updated 10 months ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆82Updated 2 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆95Updated last week
- RISC-V ISA based 32-bit processor written in HLS☆16Updated 5 years ago
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆29Updated 7 months ago
- Train and deploy LUT-based neural networks on FPGAs☆100Updated last year
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.☆86Updated 2 years ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆76Updated 3 months ago
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆66Updated last year
- ☆28Updated 3 years ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆31Updated 5 years ago
- BlackParrot on Zynq☆48Updated last week
- Verilog digital signal processing components☆158Updated 3 years ago
- Verilog Content Addressable Memory Module☆114Updated 3 years ago
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆96Updated 4 months ago
- Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…☆64Updated last year
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- ☆67Updated 4 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆66Updated 8 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 3 months ago
- AMD Xilinx University Program Vivado tutorial☆39Updated 2 years ago
- SpinalHDL Hardware Math Library☆93Updated last year
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated this week