malkadi / FGPULinks
FGPU is a soft GPU architecture general purpose computing
☆60Updated 4 years ago
Alternatives and similar repositories for FGPU
Users that are interested in FGPU are comparing it to the libraries listed below
Sorting:
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 7 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- For contributions of Chisel IP to the chisel community.☆65Updated 10 months ago
- Yet Another RISC-V Implementation☆97Updated 11 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last week
- SoCRocket - Core Repository☆38Updated 8 years ago
- Facilitates building open source tools for working with hardware description languages (HDLs)☆65Updated 5 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆46Updated 3 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- Xilinx Unisim Library in Verilog☆85Updated 5 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆88Updated 6 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆43Updated 5 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆86Updated 11 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆69Updated 8 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆119Updated 2 months ago
- A collection of big designs to run post-synthesis simulations with yosys☆50Updated 9 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆50Updated 10 months ago
- openHMC - an open source Hybrid Memory Cube Controller☆50Updated 9 years ago
- Generic FIFO implementation with optional FWFT☆60Updated 5 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆74Updated last year
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 9 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- ☆61Updated 4 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago