malkadi / FGPULinks
FGPU is a soft GPU architecture general purpose computing
☆60Updated 4 years ago
Alternatives and similar repositories for FGPU
Users that are interested in FGPU are comparing it to the libraries listed below
Sorting:
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆103Updated 6 years ago
- For contributions of Chisel IP to the chisel community.☆66Updated 10 months ago
- Yet Another RISC-V Implementation☆97Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆67Updated 7 months ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- LIS Network-on-Chip Implementation☆31Updated 9 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 3 weeks ago
- SoCRocket - Core Repository☆38Updated 8 years ago
- Xilinx Unisim Library in Verilog☆85Updated 5 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆47Updated 3 years ago
- FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.☆62Updated 9 months ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆88Updated 6 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 7 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 2 months ago
- Experiments with fixed function renderers and Chisel HDL☆59Updated 6 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆70Updated 9 months ago
- Generic FIFO implementation with optional FWFT☆60Updated 5 years ago
- Demo SoC for SiliconCompiler.☆61Updated this week
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆111Updated 2 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆74Updated last year
- A collection of big designs to run post-synthesis simulations with yosys☆50Updated 9 years ago
- ☆67Updated 2 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- ☆26Updated 5 years ago