Alternatives and similar repositories for SDKOpenGLES

Users that are interested in SDKOpenGLES are comparing it to the libraries listed below

• HarmonInstruments / verilog
  ☆20Updated 3 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆60Updated last month
• stnolting / cjtag_bridge
  🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.
  ☆24Updated 3 years ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆27Updated 3 years ago
• Efinix-Inc / xyloni
  This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board.
  ☆42Updated 2 years ago
• krtkl / snickerdoodle-hls-data-mover
  A parameterizable Vivado HLS project (C/C++) that implements a master and slave AXI-Stream to AXI-Memory-Mapped data mover (AXI-S default…
  ☆15Updated 6 years ago
• lewiz-support / LMAC_CORE1
  LMAC Core1 - Ethernet 1G/100M/10M
  ☆17Updated 2 years ago
• tomverbeure / jtag_uart_example
  Mini CPU design with JTAG UART support
  ☆20Updated 4 years ago
• hdl-util / i2c
  Fully featured implementation of Inter-IC (I2C) bus master for FPGAs
  ☆29Updated 5 years ago
• lnls-dig / general-cores
  general-cores
  ☆20Updated 3 weeks ago
• codeshaa / 16-bit-HDLC-using-VHDL
  High level Data Link Layer Control (HDLC) Protocol (16 bit) implementation using VHDL hardware description language.
  ☆29Updated 8 years ago
• BrianHGinc / Verilog-Floating-Point-Clock-Divider
  Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…
  ☆20Updated 6 months ago
• ultraembedded / core_mmc
  MMC (and derivative standards) host controller
  ☆24Updated 4 years ago
• cloudxcc / Arduissimo
  Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).
  ☆21Updated 5 years ago
• tgingold / OpenTDC
  Time to Digital Converter (TDC)
  ☆31Updated 4 years ago
• freecores / wb_builder
  WISHBONE Builder
  ☆14Updated 8 years ago
• linuxbest / ahci_mpi
  an sata controller using smallest resource.
  ☆16Updated 11 years ago
• altera-fpga / linux-refdesigns
  Source code for reference designs applications
  ☆22Updated 5 months ago
• subutai-attic / pars
  ☆30Updated 8 years ago
• TUT-ASI / leon3-grlib-gpl-mirror
  Automated Git mirror of Gaisler's GRLIB/Leon3 releases
  ☆18Updated last month
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆45Updated 5 years ago
• defparam / PCI2Nano-RTL
  An open source FPGA PCI core & 8250-Compatible PCI UART core
  ☆43Updated 4 years ago
• lawrie / tiny_ram_soc
  Picorv32 SoC that uses only BRAM, not flash memory
  ☆13Updated 6 years ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆35Updated this week
• alexforencich / pin-uart
  FPGA board-level debugging and reverse-engineering tool
  ☆38Updated 2 years ago
• nathanrossi / meta-hdl
  HDL tools layer for OpenEmbedded
  ☆17Updated 9 months ago
• watz0n / arty_xjtag
  Xilinx JTAG Toolchain on Digilent Arty board
  ☆17Updated 7 years ago
• blackmesalabs / MesaBusProtocol
  Flexible Byte transport protocol for bus bridging CPUs to FPGAs over UART,SPI,SERDES physical interfaces
  ☆34Updated 8 months ago
• Avnet / petalinux
  Repository used to support automated builds under PetaLinux tools that use Yocto.
  ☆61Updated 4 months ago
• FarisHijazi / LZ4-Decompressor-Verilog
  Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language
  ☆16Updated 6 years ago