DylanVanAssche / digitale-synthese
DSSS Wireless transmit-receive system in VHDL
☆12Updated 7 years ago
Alternatives and similar repositories for digitale-synthese:
Users that are interested in digitale-synthese are comparing it to the libraries listed below
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆48Updated last year
- A project demonstrate how to config ad9361 to TX mode and how to transmit MSK☆57Updated 5 years ago
- UART to AXI Stream interface written in VHDL☆16Updated 2 years ago
- Dual-Mode PSK Transceiver on SDR With FPGA☆30Updated 6 months ago
- An RFSoC Frequency Planner developed using Python.☆26Updated last year
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆53Updated last year
- HDL code for a complex multiplier with AXI stream interface☆16Updated 2 years ago
- A High-Throughput Oversampled Polyphase Filter Bank Using Vivado HLS and PYNQ on a RFSoC☆34Updated 7 months ago
- Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…☆65Updated 2 years ago
- RFSoC2x2 board repo for PYNQ☆17Updated 2 years ago
- RFSoC QSFP Data Offload Design with GNU Radio☆18Updated 5 months ago
- RTL implementation of components for DVB-S2☆117Updated 2 years ago
- DVB-S2 LDPC Decoder☆27Updated 10 years ago
- Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…☆85Updated 2 years ago
- FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)☆99Updated 10 months ago
- ☆33Updated 2 years ago
- development interface mil-std-1553b for system on chip☆21Updated 7 years ago
- A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC☆59Updated 3 years ago
- VHDL Library for implementing common DSP functionality.☆27Updated 6 years ago
- RFSoC Spectrum Analyser Module on PYNQ.☆77Updated 10 months ago
- PYNQ example of using the RFSoC as a QPSK/BPSK radio transceiver.☆36Updated last year
- This project aims to implement a digital predistortion algorithm for power amplifier linearizion using vhdl. It contains VHDL design for …☆16Updated 2 years ago
- OscillatorIMP ecosystem for the digital characterization of ultrastable oscillators and Software Defined Radio (SDR) frontend processing☆54Updated last month
- ☆41Updated last year
- The implementation of AD9371 on KC705☆20Updated 5 years ago
- Standalone application based on ADI hdl and no_OS for ANTSDR.☆21Updated last month
- Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS☆49Updated 2 years ago
- JESD204b modules in VHDL☆30Updated 6 years ago
- Altium Designer libraries for ANSI/VITA 57 FPGA Mezzanine Card (FMC) Standard☆43Updated 3 years ago
- PYNQ example of using the RFSoC as a QPSK transceiver.☆100Updated last year