Alternatives and similar repositories for dvb_fpga

Users that are interested in dvb_fpga are comparing it to the libraries listed below

• strath-sdr / rfsoc_qpsk
  PYNQ example of using the RFSoC as a QPSK transceiver.
  ☆105Updated 2 years ago
• catkira / open5G_phy
  A ressource efficient, customizable, synthesizable 5G NR lower PHY written in Verilog
  ☆210Updated 3 months ago
• daveshah1 / RFToolSDR
  AD9361 based USB3 SDR
  ☆115Updated 7 years ago
• dshekhalev / FEC
  FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)
  ☆115Updated last year
• ZipCPU / sdr
  A basic Soft(Gate)ware Defined Radio architecture
  ☆93Updated last year
• strath-sdr / rfsoc_ofdm
  PYNQ example of an OFDM Transmitter and Receiver on RFSoC.
  ☆50Updated 2 years ago
• oscimp / oscimpDigital
  OscillatorIMP ecosystem for the digital characterization of ultrastable oscillators and Software Defined Radio (SDR) frontend processing
  ☆57Updated last month
• Xilinx / RFSoC-PYNQ
  Python productivity for RFSoC platforms
  ☆79Updated 2 months ago
• Teddy-van-Jerry / sdr-psk-fpga
  Dual-Mode PSK Transceiver on SDR With FPGA
  ☆40Updated 10 months ago
• regymm / PYNQSDR
  PYNQ-Z1 + AD936X openwifi capable SDR platform
  ☆113Updated last month
• OpenResearchInstitute / DVB-receiver
  Work being done on the DVB-receiver for Phase 4 Ground.
  ☆58Updated 2 years ago
• analogdevicesinc / TransceiverToolbox
  MATLAB toolbox for ADI transceiver products
  ☆63Updated 5 months ago
• strath-sdr / rfsoc_frequency_planner
  An RFSoC Frequency Planner developed using Python.
  ☆30Updated 2 years ago
• srsran / zynq_timestamping
  Open source Zynq timestamping implementation from Software Radio Systems (SRS)
  ☆72Updated 2 years ago
• strath-sdr / rfsoc_sam
  RFSoC Spectrum Analyser Module on PYNQ.
  ☆84Updated last year
• open-sdr / openofdm
  Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.
  ☆119Updated last month
• MicroPhase / antsdr-pynq
  pynq framework for antsdr
  ☆36Updated last year
• dawsonjon / FPGA-radio
  Software Defined Radio in FPGA uses LVDS IO pins as 1-bit ADC
  ☆109Updated 8 years ago
• alberto-grl / 1bitSDR
  Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom
  ☆106Updated 5 years ago
• strath-sdr / rfsoc_qsfp_offload
  RFSoC QSFP Data Offload Design with GNU Radio
  ☆23Updated 9 months ago
• Xilinx / RFSoC2x2-PYNQ
  RFSoC2x2 board repo for PYNQ
  ☆17Updated 2 years ago
• hukenovs / intfftk
  Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…
  ☆88Updated 2 years ago
• owocomm-0 / fpga-fft
  A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
  ☆116Updated 4 years ago
• MicroPhase / antsdr-fw
  ANTSDR Firmware
  ☆138Updated 2 years ago
• timcardenuto / testPlutoSDR
  ☆24Updated 5 years ago
• xdsopl / LDPC
  Playing with Low-density parity-check codes
  ☆96Updated 2 years ago
• phthinh / OFDM_802_11
  IEEE 802.11 OFDM-based transceiver system
  ☆35Updated 7 years ago
• dawsonjon / FPGA-TX
  FPGA based transmitter
  ☆99Updated 8 years ago
• catkira / CIC
  HDL code for a complex multiplier with AXI stream interface
  ☆16Updated 2 years ago
• EttusResearch / fpga
  The USRP™ Hardware Driver FPGA Repository
  ☆294Updated 3 years ago