OpenResearchInstitute / dvb_fpgaLinks
RTL implementation of components for DVB-S2
☆126Updated 2 years ago
Alternatives and similar repositories for dvb_fpga
Users that are interested in dvb_fpga are comparing it to the libraries listed below
Sorting:
- AD9361 based USB3 SDR☆117Updated 8 years ago
- PYNQ example of using the RFSoC as a QPSK transceiver.☆108Updated 2 years ago
- A ressource efficient, customizable, synthesizable 5G NR lower PHY written in Verilog☆211Updated 5 months ago
- OscillatorIMP ecosystem for the digital characterization of ultrastable oscillators and Software Defined Radio (SDR) frontend processing☆58Updated this week
- FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)☆121Updated last year
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆53Updated 2 years ago
- A basic Soft(Gate)ware Defined Radio architecture☆94Updated last year
- Open source Zynq timestamping implementation from Software Radio Systems (SRS)☆73Updated 2 years ago
- pynq framework for antsdr☆36Updated last year
- Work being done on the DVB-receiver for Phase 4 Ground.☆58Updated 2 years ago
- PYNQ-Z1 + AD936X openwifi capable SDR platform☆117Updated 3 months ago
- MATLAB toolbox for ADI transceiver products☆62Updated 6 months ago
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆56Updated last year
- Software Defined Radio in FPGA uses LVDS IO pins as 1-bit ADC☆110Updated 8 years ago
- ☆24Updated 5 years ago
- Python productivity for RFSoC platforms☆80Updated last week
- RFSoC QSFP Data Offload Design with GNU Radio☆24Updated 10 months ago
- Dual-Mode PSK Transceiver on SDR With FPGA☆44Updated 11 months ago
- RFSoC Spectrum Analyser Module on PYNQ.☆87Updated last year
- Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.☆118Updated 2 months ago
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆120Updated 4 years ago
- An RFSoC Frequency Planner developed using Python.☆31Updated 2 years ago
- IIO AD9361 library for filter design and handling, multi-chip sync, etc.☆92Updated last week
- FPGA based transmitter☆99Updated 8 years ago
- Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom☆106Updated 5 years ago
- The USRP™ Hardware Driver FPGA Repository☆292Updated 3 years ago
- RFSoC2x2 board repo for PYNQ☆17Updated 2 years ago
- Companion Jupyter Notebooks for the RFSoC-Book.☆231Updated 2 years ago
- HDL code for a complex multiplier with AXI stream interface☆16Updated 2 years ago
- ANTSDR Firmware☆136Updated 2 years ago