casper-astro / casperfpgaLinks
Software control for CASPER FPGAs
☆22Updated 4 months ago
Alternatives and similar repositories for casperfpga
Users that are interested in casperfpga are comparing it to the libraries listed below
Sorting:
- An RFSoC Frequency Planner developed using Python.☆31Updated 2 years ago
- The Strathclyde RFSoC Studio Installer for PYNQ.☆35Updated 2 years ago
- Python productivity for RFSoC platforms☆85Updated 2 months ago
- Tutorials available here:☆37Updated 4 months ago
- Board repo for the ZCU216 RFSOC☆31Updated 3 years ago
- RFSoC2x2 board repo for PYNQ☆17Updated 3 years ago
- RFSoC Spectrum Analyser Module on PYNQ.☆90Updated this week
- PYNQ example of using the RFSoC as a QPSK transceiver.☆109Updated 2 years ago
- Firmware that implements a reliable high-performance control link for particle physics electronics, based on the IPbus protocol☆43Updated last month
- A PYNQ overlay demonstrating the Xilinx RFSoC SD-FEC☆13Updated 3 years ago
- ☆19Updated 4 years ago
- Open-sourcing the PYNQ & RFSoC workshop materials☆63Updated 5 years ago
- RFSoC QSFP Data Offload Design with GNU Radio☆25Updated last year
- PYNQ example of using the RFSoC as a QPSK/BPSK radio transceiver.☆40Updated 2 years ago
- ☆46Updated last month
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆108Updated this week
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆59Updated this week
- A High-Throughput Oversampled Polyphase Filter Bank Using Vivado HLS and PYNQ on a RFSoC☆41Updated last year
- A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS).☆32Updated 2 years ago
- Demonstration of Automatic Gain Control with PYNQ☆17Updated 3 years ago
- Gaussian noise generator Verilog IP core☆32Updated 2 years ago
- Digital systems are clocked. This project is about constructing a high-Q clock by simmering an ordinary quartz crystal in a heavy numeric…☆22Updated this week
- ☆30Updated 4 years ago
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆59Updated last year
- Serial communication link bit error rate tester simulator, written in Python.☆120Updated 3 weeks ago
- Small footprint and configurable JESD204B core☆50Updated 3 months ago
- A basic Soft(Gate)ware Defined Radio architecture☆100Updated 2 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆39Updated 10 months ago
- Digital Signal Processing and Well-Known Modulations on HDL☆41Updated 7 months ago
- A tool for merging the MyHDL workflow with Vivado☆20Updated 5 years ago