Alternatives and similar repositories for neorv32-freertos

Users that are interested in neorv32-freertos are comparing it to the libraries listed below

• stnolting / neorv32-setups
  📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
  ☆83Updated last week
• tinylabs / tinylabs-cores
  Fusesoc compatible rtl cores
  ☆15Updated 2 years ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆95Updated this week
• qermit / WishboneAXI
  Wishbone to AXI bridge (VHDL)
  ☆42Updated 6 years ago
• ZipCPU / interpolation
  Digital Interpolation Techniques Applied to Digital Signal Processing
  ☆63Updated last year
• Isotel / mixedsim
  Hardware Design Tool - Mixed Signal Simulation with Verilog
  ☆84Updated 9 months ago
• davemuscle / sigma_delta_converters
  Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components
  ☆74Updated 3 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆118Updated last year
• ZipCPU / dspfilters
  A collection of demonstration digital filters
  ☆154Updated last year
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆106Updated 3 weeks ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆23Updated last year
• chili-chips-ba / openCologne
  Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…
  ☆71Updated 3 weeks ago
• amaranth-lang / amaranth-boards
  Board definitions for Amaranth HDL
  ☆118Updated 3 weeks ago
• SanDisk-Open-Source / pyvcd
  Python package for writing Value Change Dump (VCD) files.
  ☆123Updated 10 months ago
• amaranth-farm / amlib
  assorted library of utility cores for amaranth HDL
  ☆96Updated last year
• hdl / pyHDLParser
  Simple Python parser for extracting HDL (VHDL or Verilog) documentation
  ☆22Updated last year
• wavedrom / vcd-samples
  sample VCD files
  ☆37Updated last week
• openXC7 / demo-projects
  Demo projects for various Kintex FPGA boards
  ☆62Updated 4 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆147Updated 4 months ago
• no2fpga / no2usb
  Nitro USB FPGA core
  ☆87Updated last year
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆34Updated this week
• leonow32 / verilog-fpga
  Many peripherals in Verilog ready to use
  ☆39Updated 8 months ago
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆80Updated 5 years ago
• Efinix-Inc / xyloni
  This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board.
  ☆42Updated 2 years ago
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆50Updated 6 months ago
• BerkeleyLab / XVC-FTDI-JTAG
  Xilinx virtual cable server for generic FTDI 4232H.
  ☆59Updated last year
• olgirard / openmsp430
  The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
  ☆65Updated 7 years ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆125Updated 6 years ago
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆92Updated 11 months ago
• smunaut / iCE40linux
  Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker
  ☆101Updated 2 years ago