stnolting / neorv32-freertosLinks
💾 FreeRTOS port for the NEORV32 RISC-V Processor.
☆11Updated this week
Alternatives and similar repositories for neorv32-freertos
Users that are interested in neorv32-freertos are comparing it to the libraries listed below
Sorting:
- 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.☆86Updated this week
- Fusesoc compatible rtl cores☆15Updated 3 years ago
- ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.☆38Updated last week
- This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board.☆45Updated 2 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆101Updated last month
- ArtyS7-50 VexRiscV LiteX SoC using multiple Ethernet Interface☆18Updated 5 years ago
- PID controller☆24Updated 11 years ago
- Tiny Tapeout project build tools + chip integration scripts☆28Updated 3 weeks ago
- Some neorv32 examples for Intel FPGA boards using Quartus II and SEGGER Embedded Studio for RISC-V.☆15Updated 3 months ago
- Demo projects for various Kintex FPGA boards☆65Updated 7 months ago
- ☆15Updated last year
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆109Updated 3 weeks ago
- A LiteX module implementing a USB UAC2 module with simple PDM in/out☆16Updated 3 years ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 4 years ago
- Wishbone to AXI bridge (VHDL)☆44Updated 6 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆70Updated 7 years ago
- Open Source FPGA toolchain and documentation for QuickLogic devices and eFPGA IP☆40Updated 4 years ago
- Altium Designer libraries for ANSI/VITA 57 FPGA Mezzanine Card (FMC) Standard☆45Updated 4 years ago
- ☆38Updated last month
- Small footprint and configurable JESD204B core☆50Updated 2 months ago
- Using VexRiscv without installing Scala☆39Updated 4 years ago
- Featherweight RISC-V implementation☆53Updated 3 years ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆85Updated 2 months ago
- System on Chip toolkit for Amaranth HDL☆97Updated last year
- FPGA based microcomputer sandbox for software and RTL experimentation☆75Updated 2 weeks ago
- FPGA examples on Google Colab☆27Updated 4 months ago
- Nitro USB FPGA core☆86Updated last year
- Small footprint and configurable Inter-Chip communication cores☆66Updated 2 months ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆46Updated this week
- Parametric GPIO Peripheral☆11Updated 11 months ago