π Add capacitive touch buttons to any FPGA!
β105Mar 4, 2022Updated 4 years ago
Alternatives and similar repositories for captouch
Users that are interested in captouch are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.β16Apr 10, 2025Updated last year
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workβ¦β10Jan 13, 2022Updated 4 years ago
- Standard and Curated cores, tested and working.β11Dec 29, 2022Updated 3 years ago
- GitHub-based statistics highlighting interesting facts about the HDL industryβ12Jul 6, 2023Updated 2 years ago
- π₯ Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.β33Aug 20, 2022Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer β’ AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- VHDL related news.β27Updated this week
- Interfacing VHDL and foreign languages with VUnitβ15Feb 20, 2020Updated 6 years ago
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 featuresβ32Jan 30, 2025Updated last year
- Support for automatic address map generation and address decoding logic for Wishbone connected hierachical systemsβ12Mar 12, 2026Updated 3 months ago
- A first approach of getting a pure Ada program running on an FPGA with SaxonSOCβ10Apr 12, 2021Updated 5 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boardsβ48Feb 12, 2026Updated 4 months ago
- ulx3s ghdl examplesβ15Mar 6, 2021Updated 5 years ago
- β11Feb 23, 2026Updated 4 months ago
- a project to check the FOSS synthesizers against vendors EDA toolsβ12Sep 26, 2020Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer β’ AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- This repository is an excuse to learn about Convolutional Neural Networks by implementing one in FPGA. The main goal is to learn, and to β¦β12Jul 12, 2020Updated 5 years ago
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.β14Feb 24, 2026Updated 4 months ago
- Experiments with Cologne Chip's GateMate FPGA architectureβ19Nov 16, 2023Updated 2 years ago
- Building and deploying container images for open source electronic design automation (EDA)β123Oct 3, 2024Updated last year
- Generator for VHDL regular expression matchersβ15Jan 11, 2021Updated 5 years ago
- π² A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).β220Jun 22, 2026Updated last week
- PNG encoder, implemented in VHDLβ23Mar 30, 2024Updated 2 years ago
- π NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.β96Jun 23, 2026Updated last week
- Python API to Unified Coverage Interoperability Standard (UCIS) Dataβ35Mar 7, 2026Updated 3 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer β’ AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDLβ52Updated this week
- Virtual development board for HDL designβ42Mar 31, 2023Updated 3 years ago
- Fixed point package for Python.β37Apr 28, 2023Updated 3 years ago
- Deprecated - This library has been replaced by OsvvmLibraries. The links to the submodules will not be updated to the new versions.β10Jul 22, 2020Updated 5 years ago
- ASCII art figures can be parsed and output as SVG, PNG, JPEG, PDF and more. This project provides a python package and a command line scrβ¦β21Jul 5, 2017Updated 8 years ago
- An open source, parameterized SystemVerilog digital hardware IP libraryβ33May 26, 2024Updated 2 years ago
- User-friendly explanation of Yosys optionsβ113Sep 25, 2021Updated 4 years ago
- VHDL String Formatting Libraryβ27Apr 27, 2024Updated 2 years ago
- β17Nov 25, 2017Updated 8 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer β’ AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Repo to help explain the different options users have for packaging.β19Jun 8, 2022Updated 4 years ago
- Example of Test Driven Design with VUnitβ16Nov 22, 2021Updated 4 years ago
- Specification of the Wishbone SoC Interconnect Architectureβ54Jun 5, 2022Updated 4 years ago
- Examples and design pattern for VHDL verificationβ15Apr 10, 2016Updated 10 years ago
- A tool for modeling FSMs by VHDL or Verilogβ14Updated this week
- Cross EDA Abstraction and Automationβ41Nov 17, 2025Updated 7 months ago
- A hardware model checker for hyperpropertiesβ18Jun 14, 2024Updated 2 years ago