stnolting / captouch
👇 Add capacitive touch buttons to any FPGA!
☆103Updated 2 years ago
Alternatives and similar repositories for captouch:
Users that are interested in captouch are comparing it to the libraries listed below
- Hardware definition language that compiles to Verilog☆106Updated 3 years ago
- Documenting Lattice's 28nm FPGA parts☆142Updated last year
- A bit-serial CPU written in VHDL, with a simulator written in C.☆124Updated 5 months ago
- WIP 100BASE-TX PHY☆74Updated 2 months ago
- 🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).☆21Updated 3 years ago
- Virtual Development Board☆58Updated 3 years ago
- User-friendly explanation of Yosys options☆112Updated 3 years ago
- Small footprint and configurable embedded FPGA logic analyzer☆172Updated 2 weeks ago
- Copyleftist's Standard Cell Library☆98Updated 9 months ago
- Glacial - microcoded RISC-V core designed for low FPGA resource utilization☆83Updated 5 years ago
- ☆77Updated 11 months ago
- Logicbone ECP5 Development Board☆114Updated 4 years ago
- Board definitions for Amaranth HDL☆108Updated 2 weeks ago
- Bootloader for Fomu☆101Updated 2 years ago
- Small footprint and configurable Ethernet core☆223Updated last week
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 2 years ago
- CoreScore☆143Updated 3 weeks ago
- Playground for VGA projects on Tiny Tapeout☆59Updated 2 weeks ago
- FPGA USB stack written in LiteX☆126Updated 2 years ago
- Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)☆32Updated 3 years ago
- My own FPGA architecture simulated in VHDL, realized with 7400-logic on PCB.☆41Updated 10 months ago
- Demo SoC for SiliconCompiler.☆56Updated last month
- Naive Educational RISC V processor☆78Updated 4 months ago
- Ultimate ECP5 development board☆104Updated 5 years ago
- Small footprint and configurable video cores (Deprecated)☆71Updated 3 years ago
- A template project for the ULX3S ECP5 FPGA board using only Open Source Software☆13Updated 6 years ago
- Experiments with Yosys cxxrtl backend☆47Updated last month
- A configurable and approachable tool for FPGA debugging and rapid prototyping.☆126Updated 2 months ago
- Specification of the Wishbone SoC Interconnect Architecture☆42Updated 2 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆67Updated 2 years ago