👇 Add capacitive touch buttons to any FPGA!
☆102Mar 4, 2022Updated 4 years ago
Alternatives and similar repositories for captouch
Users that are interested in captouch are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.☆16Apr 10, 2025Updated last year
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Jan 13, 2022Updated 4 years ago
- Standard and Curated cores, tested and working.☆11Dec 29, 2022Updated 3 years ago
- GitHub-based statistics highlighting interesting facts about the HDL industry☆12Jul 6, 2023Updated 2 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆32Aug 20, 2022Updated 3 years ago
- Wordpress hosting with auto-scaling on Cloudways • AdFully Managed hosting built for WordPress-powered businesses that need reliable, auto-scalable hosting. Cloudways SafeUpdates now available.
- VHDL related news.☆27Updated this week
- Interfacing VHDL and foreign languages with VUnit☆15Feb 20, 2020Updated 6 years ago
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆32Jan 30, 2025Updated last year
- Support for automatic address map generation and address decoding logic for Wishbone connected hierachical systems☆12Mar 12, 2026Updated last month
- A first approach of getting a pure Ada program running on an FPGA with SaxonSOC☆10Apr 12, 2021Updated 5 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆47Feb 12, 2026Updated 2 months ago
- ulx3s ghdl examples☆15Mar 6, 2021Updated 5 years ago
- Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.☆13Sep 22, 2025Updated 6 months ago
- a project to check the FOSS synthesizers against vendors EDA tools☆12Sep 26, 2020Updated 5 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- This repository is an excuse to learn about Convolutional Neural Networks by implementing one in FPGA. The main goal is to learn, and to …☆12Jul 12, 2020Updated 5 years ago
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.☆14Feb 24, 2026Updated last month
- Experiments with Cologne Chip's GateMate FPGA architecture☆17Nov 16, 2023Updated 2 years ago
- Building and deploying container images for open source electronic design automation (EDA)☆121Oct 3, 2024Updated last year
- Generator for VHDL regular expression matchers☆15Jan 11, 2021Updated 5 years ago
- 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).☆217Apr 1, 2026Updated last week
- PNG encoder, implemented in VHDL☆23Mar 30, 2024Updated 2 years ago
- 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.☆90Apr 6, 2026Updated last week
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆32Mar 7, 2026Updated last month
- Wordpress hosting with auto-scaling on Cloudways • AdFully Managed hosting built for WordPress-powered businesses that need reliable, auto-scalable hosting. Cloudways SafeUpdates now available.
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆52Apr 5, 2026Updated last week
- Virtual development board for HDL design☆42Mar 31, 2023Updated 3 years ago
- A linux'ish build system for System on Chip designs, based on GHDL☆12Dec 14, 2024Updated last year
- Fixed point package for Python.☆36Apr 28, 2023Updated 2 years ago
- Deprecated - This library has been replaced by OsvvmLibraries. The links to the submodules will not be updated to the new versions.☆10Jul 22, 2020Updated 5 years ago
- ASCII art figures can be parsed and output as SVG, PNG, JPEG, PDF and more. This project provides a python package and a command line scr…☆21Jul 5, 2017Updated 8 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆33May 26, 2024Updated last year
- User-friendly explanation of Yosys options☆113Sep 25, 2021Updated 4 years ago
- VHDL String Formatting Library☆27Apr 27, 2024Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- ☆17Nov 25, 2017Updated 8 years ago
- Repo to help explain the different options users have for packaging.☆19Jun 8, 2022Updated 3 years ago
- Example of Test Driven Design with VUnit☆16Nov 22, 2021Updated 4 years ago
- A flexible framework for analyzing and transforming FPGA netlists. Official repository.☆111Feb 12, 2025Updated last year
- Specification of the Wishbone SoC Interconnect Architecture☆52Jun 5, 2022Updated 3 years ago
- Examples and design pattern for VHDL verification☆15Apr 10, 2016Updated 10 years ago
- A tool for modeling FSMs by VHDL or Verilog☆12Updated this week