π Add capacitive touch buttons to any FPGA!
β102Mar 4, 2022Updated 4 years ago
Alternatives and similar repositories for captouch
Users that are interested in captouch are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.β16Apr 10, 2025Updated 11 months ago
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workβ¦β10Jan 13, 2022Updated 4 years ago
- Standard and Curated cores, tested and working.β11Dec 29, 2022Updated 3 years ago
- GitHub-based statistics highlighting interesting facts about the HDL industryβ12Jul 6, 2023Updated 2 years ago
- π₯ Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.β32Aug 20, 2022Updated 3 years ago
- VHDL related news.β27Updated this week
- Interfacing VHDL and foreign languages with VUnitβ15Feb 20, 2020Updated 6 years ago
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 featuresβ32Jan 30, 2025Updated last year
- Support for automatic address map generation and address decoding logic for Wishbone connected hierachical systemsβ12Mar 12, 2026Updated last week
- A first approach of getting a pure Ada program running on an FPGA with SaxonSOCβ10Apr 12, 2021Updated 4 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boardsβ47Feb 12, 2026Updated last month
- ulx3s ghdl examplesβ15Mar 6, 2021Updated 5 years ago
- Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.β13Sep 22, 2025Updated 6 months ago
- β11Feb 23, 2026Updated last month
- a project to check the FOSS synthesizers against vendors EDA toolsβ12Sep 26, 2020Updated 5 years ago
- This repository is an excuse to learn about Convolutional Neural Networks by implementing one in FPGA. The main goal is to learn, and to β¦β12Jul 12, 2020Updated 5 years ago
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.β14Feb 24, 2026Updated last month
- Experiments with Cologne Chip's GateMate FPGA architectureβ17Nov 16, 2023Updated 2 years ago
- Building and deploying container images for open source electronic design automation (EDA)β121Oct 3, 2024Updated last year
- Generator for VHDL regular expression matchersβ15Jan 11, 2021Updated 5 years ago
- π² A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).β215Nov 26, 2025Updated 3 months ago
- PNG encoder, implemented in VHDLβ23Mar 30, 2024Updated last year
- π NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.β89Mar 9, 2026Updated 2 weeks ago
- Python API to Unified Coverage Interoperability Standard (UCIS) Dataβ31Mar 7, 2026Updated 2 weeks ago
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL