stanford-ppl / spatial-langLinks
Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"
☆101Updated 6 years ago
Alternatives and similar repositories for spatial-lang
Users that are interested in spatial-lang are comparing it to the libraries listed below
Sorting:
- Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"☆282Updated last year
- Quickstart for Spatial language☆34Updated 4 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 5 years ago
- Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…☆56Updated 4 years ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆209Updated 5 years ago
- ☆389Updated 7 years ago
- The Delite Git Repo☆221Updated 8 years ago
- ☆58Updated 8 years ago
- Chisel/Firrtl execution engine☆153Updated 9 months ago
- The Shang high-level synthesis framework☆119Updated 11 years ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Updated 7 years ago
- HLS branch of Halide☆76Updated 6 years ago
- Floating point modules for CHISEL☆32Updated 10 years ago
- ☆15Updated 8 years ago
- A scala based simulator for circuits described by a LoFirrtl file☆48Updated 2 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆154Updated last year
- ☆87Updated 2 years ago
- Chisel components for FPGA projects☆124Updated last year
- Time-sensitive affine types for predictable hardware generation☆143Updated 10 months ago
- Scala staging framework☆16Updated 6 years ago
- A Library of Chisel3 Tools for Digital Signal Processing☆236Updated last year
- ☆15Updated 2 years ago
- Reference workloads for modern deep learning methods.☆73Updated 2 years ago
- Provides Spatial with front-end support from popular machine learning frameworks☆33Updated 5 years ago
- Repository for the tools and non-commercial data used for the "Accelerator wall" paper.☆50Updated 6 years ago
- Create auto-scheduled data-parallel pipelines in hardware with user-friendly Python☆13Updated 4 years ago
- ☆40Updated 3 years ago
- DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language☆85Updated 3 weeks ago
- Useful utilities for BAR projects☆31Updated last year
- Connectal is a framework for software-driven hardware development.☆170Updated last year