Alternatives and similar repositories for spatial-lang

Users that are interested in spatial-lang are comparing it to the libraries listed below

• stanford-ppl / spatial
  Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"
  ☆283Updated last year
• ucb-bar / midas
  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  ☆101Updated 5 years ago
• stanford-ppl / spatial-quickstart
  Quickstart for Spatial language
  ☆34Updated 4 years ago
• bu-icsg / dana
  Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
  ☆211Updated 5 years ago
• jameshegarty / rigel
  Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…
  ☆56Updated 4 years ago
• chipsalliance / treadle
  Chisel/Firrtl execution engine
  ☆153Updated 10 months ago
• ucb-bar / chisel2-deprecated
  ☆389Updated 7 years ago
• maltanar / fpga-tidbits
  Chisel components for FPGA projects
  ☆124Updated last year
• scale-lab / la-core
  Linear algebra accelerators for RISC-V (published in ICCD 17)
  ☆66Updated 7 years ago
• zhemao / chisel-float
  Floating point modules for CHISEL
  ☆32Updated 10 years ago
• ucb-bar / dsptools
  A Library of Chisel3 Tools for Digital Signal Processing
  ☆236Updated last year
• stanford-ppl / Delite
  The Delite Git Repo
  ☆221Updated 8 years ago
• cucapra / dahlia
  Time-sensitive affine types for predictable hardware generation
  ☆143Updated 11 months ago
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆74Updated 6 years ago
• google / bottlerocket
  ☆109Updated 6 years ago
• intel / rapid-design-methods-for-developing-hardware-accelerators
  ☆87Updated 2 years ago
• OPAE / intel-fpga-bbb
  Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
  ☆104Updated 4 months ago
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆119Updated 2 years ago
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆100Updated 2 years ago
• stanford-ppl / hyperdsl
  ☆58Updated 8 years ago
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆154Updated last year
• PrincetonUniversity / accelerator-wall
  Repository for the tools and non-commercial data used for the "Accelerator wall" paper.
  ☆50Updated 6 years ago
• etherzhhb / Shang
  The Shang high-level synthesis framework
  ☆120Updated 11 years ago
• jingpu / Halide-HLS
  HLS branch of Halide
  ☆77Updated 6 years ago
• firesim / FireMarshal
  Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.
  ☆82Updated 3 weeks ago
• cambridgehackers / connectal
  Connectal is a framework for software-driven hardware development.
  ☆170Updated last year
• LBL-CoDEx / OpenSoCFabric
  OpenSoC Fabric - A Network-On-Chip Generator
  ☆169Updated 5 years ago
• freechipsproject / firrtl-interpreter
  A scala based simulator for circuits described by a LoFirrtl file
  ☆48Updated 2 years ago
• rdaly525 / coreir
  ☆103Updated 2 years ago
• rdadolf / fathom
  Reference workloads for modern deep learning methods.
  ☆73Updated 2 years ago