suisuisi / EBAZ4205Links
EBAZ4205 is Xilinx Zynq based mining board used in Ebang Ebit E9+ bitcoin miner machine.
☆10Updated 3 years ago
Alternatives and similar repositories for EBAZ4205
Users that are interested in EBAZ4205 are comparing it to the libraries listed below
Sorting:
- 基于arm cortex-m0内核的xillinx fpga sopc工程项目☆13Updated 6 years ago
- USB 2.0 Device IP Core☆68Updated 7 years ago
- FPGA Technology Exchange Group相关文件管理☆51Updated 2 weeks ago
- Delta-sigma ADC,PDM audio FPGA Implementation☆72Updated 3 years ago
- - Use FPGA to implement MIPI interface; - Get command from PC through USB communication; - Decode command in FPGA☆12Updated 8 years ago
- Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS☆54Updated 2 years ago
- FPGA和USB3.0桥片实现USB3.0通信☆72Updated 3 years ago
- VHDL code for using Xilnx LVDS lines for MIPI CSI-2 TX protocol. For educational purposes☆74Updated 2 years ago
- It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.☆74Updated last year
- Cortex_m0软核源码,可以在FPGA上直接跑,包含UART、定时器这些外设,可以用keil写用户代码。可以看看《Cortex-M0 全可编程SoC原理及实现》这本书☆25Updated 4 years ago
- SPI Slave for FPGA in Verilog and VHDL☆212Updated last year
- SPI-Flash XIP Interface (Verilog)☆45Updated 3 years ago
- A Voila-Jones face detector hardware implementation☆32Updated 6 years ago
- ☆21Updated 3 years ago
- ☆31Updated 5 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆33Updated 5 years ago
- 平头哥无剑100开源SoC平台(双核E902,安全启动,BootROM,IOPMP,Mailbox,RSA-2048,SHA-2, WS2812,Flash)☆21Updated 2 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- Interface Protocol in Verilog☆50Updated 6 years ago
- I2C Master and Slave☆37Updated 10 years ago
- QSPI for SoC☆22Updated 5 years ago
- 8051 core☆107Updated 11 years ago
- MIPI CSI-2 Camera Sensor Receiver V2 Verilog HDL implementation For any generic FPGA. Tested with IMX219 IMX477 on Lattice Crosslink NX w…☆58Updated 7 months ago
- Peripheral Interface of FPGA☆40Updated 4 years ago
- Basic USB-CDC device core (Verilog)☆80Updated 4 years ago
- fpga based nes box☆32Updated 3 years ago
- Cortex M0 based SoC☆75Updated 4 years ago
- SEA-S7_gesture recognition☆17Updated 5 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆63Updated 4 years ago
- Verilog SPI master and slave☆59Updated 9 years ago