hal-uw / cpelide-micro24-artifactLinks
This GitHub repo contains the artifact for CPElide, which appears at MICRO '24
☆11Updated 10 months ago
Alternatives and similar repositories for cpelide-micro24-artifact
Users that are interested in cpelide-micro24-artifact are comparing it to the libraries listed below
Sorting:
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆41Updated last year
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆69Updated 4 months ago
- STONNE: A Simulation Tool for Neural Networks Engines☆133Updated last month
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆37Updated 2 years ago
- HyFiSS: A Hybrid Fidelity Stall-Aware Simulator for GPGPUs☆35Updated 7 months ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆84Updated 2 months ago
- ☆34Updated last month
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆58Updated 7 months ago
- ☆77Updated last year
- A dataflow architecture for universal graph neural network inference via multi-queue streaming.☆73Updated 2 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆68Updated last year
- An analytical framework that models hardware dataflow of tensor applications on spatial architectures using the relation-centric notation…☆86Updated last year
- NeuPIMs: NPU-PIM Heterogeneous Acceleration for Batched LLM Inferencing☆87Updated last year
- PIMeval simulator and PIMbench suite☆32Updated this week
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆55Updated 4 years ago
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆65Updated 2 years ago
- Release of stream-specialization software/hardware stack.☆122Updated 2 years ago
- ☆56Updated 3 months ago
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆133Updated 5 months ago
- MICRO22 artifact evaluation for Sparseloop☆45Updated 2 years ago
- A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0☆28Updated 5 months ago
- ☆28Updated 3 years ago
- ☆144Updated 5 months ago
- PUMA Compiler☆29Updated 5 years ago
- Processing-In-Memory (PIM) Simulator☆174Updated 7 months ago
- RTL implementation of Flex-DPE.☆106Updated 5 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆54Updated 3 months ago
- agile hardware-software co-design☆50Updated 3 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆82Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆93Updated 9 months ago