hal-uw / cpelide-micro24-artifactLinks
This GitHub repo contains the artifact for CPElide, which appears at MICRO '24
☆11Updated 11 months ago
Alternatives and similar repositories for cpelide-micro24-artifact
Users that are interested in cpelide-micro24-artifact are comparing it to the libraries listed below
Sorting:
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆38Updated 2 years ago
- HyFiSS: A Hybrid Fidelity Stall-Aware Simulator for GPGPUs☆36Updated 8 months ago
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆69Updated 5 months ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆68Updated last year
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆65Updated 2 years ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆86Updated 3 months ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆60Updated 8 months ago
- ☆38Updated 2 months ago
- MICRO22 artifact evaluation for Sparseloop☆44Updated 3 years ago
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆42Updated last year
- STONNE: A Simulation Tool for Neural Networks Engines☆137Updated last month
- ☆77Updated last year
- NeuPIMs: NPU-PIM Heterogeneous Acceleration for Batched LLM Inferencing☆89Updated last year
- Release of stream-specialization software/hardware stack.☆121Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated 10 months ago
- A dataflow architecture for universal graph neural network inference via multi-queue streaming.☆73Updated 2 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆82Updated last year
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆55Updated 4 years ago
- PIMeval simulator and PIMbench suite☆32Updated last week
- ☆28Updated 3 years ago
- A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0☆30Updated 3 weeks ago
- ☆56Updated 4 months ago
- ☆30Updated 9 months ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆60Updated 4 months ago
- Artifact material for [HPCA 2025] #2108 "UniNDP: A Unified Compilation and Simulation Tool for Near DRAM Processing Architectures"☆37Updated 8 months ago
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆138Updated 6 months ago
- ☆146Updated 6 months ago
- An analytical framework that models hardware dataflow of tensor applications on spatial architectures using the relation-centric notation…☆86Updated last year
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆147Updated 2 months ago
- RTL implementation of Flex-DPE.☆108Updated 5 years ago