Alternatives and similar repositories for riscv-ime-extension-spec:

Users that are interested in riscv-ime-extension-spec are comparing it to the libraries listed below

• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆82Updated 3 weeks ago
• riscv / riscv-bfloat16
  ☆34Updated 9 months ago
• riscv / riscv-aia
  ☆89Updated last month
• XUANTIE-RV / xuantie-gnu-toolchain
  GNU toolchain for Xuantie RISC-V CPU, including GCC and Binutils ……
  ☆98Updated last week
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆138Updated 2 months ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆93Updated last week
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆114Updated 4 months ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆65Updated 9 months ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆105Updated this week
• riscv-stc / riscv-matrix-spec
  RISC-V Matrix Specification
  ☆21Updated 4 months ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆79Updated 2 weeks ago
• camel-cdr / rvv-bench
  A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
  ☆110Updated last month
• OpenXiangShan / YunSuan
  This repo includes XiangShan's function units
  ☆18Updated last week
• hushenwei2000 / rvv-atg
  RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…
  ☆14Updated last year
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆70Updated last year
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆143Updated last year
• RISCVtestbed / rvv-rollback
  Translate RISC-V Vector Assembly from v1.0 to v0.7
  ☆33Updated 8 months ago
• pulp-platform / redmule
  ☆57Updated this week
• XUANTIE-RV / csi-nn2
  An optimized neural network operator library for chips base on Xuantie CPU.
  ☆90Updated 9 months ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆65Updated 5 years ago
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆175Updated last week
• tum-ei-eda / muriscv-nn
  muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.
  ☆76Updated last month
• plctlab / rvv-benchmark
  PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases
  ☆22Updated 4 years ago
• tenstorrent / whisper
  ☆41Updated last month
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• riscvarchive / riscv-aclint
  ☆42Updated 3 years ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆91Updated 3 weeks ago
• THU-DSP-LAB / llvm-project
  LLVM OpenCL C compiler suite for ventus GPGPU
  ☆45Updated 2 weeks ago
• riscv-non-isa / tg-nexus-trace
  RISC-V Nexus Trace TG documentation and reference code
  ☆50Updated 3 months ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆89Updated 3 weeks ago