IntelLabs / riscv-vectorLinks
Vector Acceleration IP core for RISC-V*
☆184Updated 5 months ago
Alternatives and similar repositories for riscv-vector
Users that are interested in riscv-vector are comparing it to the libraries listed below
Sorting:
- Chisel RISC-V Vector 1.0 Implementation☆114Updated 2 weeks ago
- Unit tests generator for RVV 1.0☆92Updated last month
- A Chisel RTL generator for network-on-chip interconnects☆212Updated 2 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆122Updated 2 weeks ago
- Open source high performance IEEE-754 floating unit☆85Updated last year
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆180Updated last week
- high-performance RTL simulator☆180Updated last year
- An energy-efficient RISC-V floating-point compute cluster.☆113Updated this week
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆155Updated last year
- Vector processor for RISC-V vector ISA☆129Updated 5 years ago
- A Fast, Low-Overhead On-chip Network☆231Updated last week
- A matrix extension proposal for AI applications under RISC-V architecture☆153Updated 8 months ago
- A dynamic verification library for Chisel.☆156Updated 11 months ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆184Updated last month
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆112Updated 2 years ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆108Updated 5 months ago
- ☆59Updated last week
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆133Updated 3 weeks ago
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆232Updated last year
- Open-source RTL logic simulator with CUDA acceleration☆222Updated 3 weeks ago
- Modeling Architectural Platform☆211Updated this week
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆104Updated last month
- Open-source high-performance non-blocking cache☆90Updated last month
- RISC-V Torture Test☆200Updated last year
- RiVEC Bencmark Suite☆123Updated 10 months ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- Tile based architecture designed for computing efficiency, scalability and generality☆269Updated last month
- chipyard in mill :P☆77Updated last year
- Open-source non-blocking L2 cache☆50Updated this week