rwpenney / spfpmLinks
Package for performing fixed-point, arbitrary-precision arithmetic in Python.
☆66Updated last year
Alternatives and similar repositories for spfpm
Users that are interested in spfpm are comparing it to the libraries listed below
Sorting:
- Hot & Spicy tool suite☆23Updated 3 years ago
- A python library for fractional fixed-point (base 2) arithmetic and binary manipulation with Numpy compatibility.☆200Updated last year
- A Vivado HLS Command Line Helper Tool☆36Updated 4 years ago
- Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).☆61Updated 3 years ago
- ☆83Updated 5 years ago
- Tutorial for integrating PyMTL and Vivado HLS☆19Updated 9 years ago
- ☆35Updated 6 years ago
- HW Design: A Functional Approach☆147Updated 2 years ago
- Fixed point arithmetic python package☆38Updated last year
- Python interface to FPGA interchange format☆41Updated 3 years ago
- A collection of awesome MyHDL tutorials, projects and third-party tools.☆93Updated 4 years ago
- Jupyter notebook examples on image classification with quantized neural networks☆70Updated 5 years ago
- ☆109Updated 6 years ago
- Algorithmic C Math Library☆65Updated 5 months ago
- This repo is for ECE44x (Fall2015-Spring2016)☆20Updated 7 years ago
- Python tools for Vivado Projects☆72Updated 6 years ago
- VHDL-2008 Support Library☆57Updated 9 years ago
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆49Updated 4 years ago
- Linear model training using stochastic gradient descent (SGD) on PYNQ with full to low precision.☆55Updated 7 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆34Updated 7 years ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆67Updated 8 years ago
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Updated 6 years ago
- Networking Overlay on PYNQ☆50Updated 6 years ago
- A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Si…☆291Updated last week
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆218Updated 5 years ago
- The Shang high-level synthesis framework☆120Updated 11 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- Python wrapper for verilator model☆92Updated last year
- Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.☆101Updated 9 months ago
- Verification Utilities for MyHDL☆17Updated 2 years ago