rwpenney / spfpm

Related projects ⓘ

Alternatives and complementary repositories for spfpm

• smlgit / fpbinary
  Fixed point package for Python.
  ☆34Updated last year
• benjmarshall / hlsclt
  A Vivado HLS Command Line Helper Tool
  ☆36Updated 3 years ago
• francof2a / fxpmath
  A python library for fractional fixed-point (base 2) arithmetic and binary manipulation with Numpy compatibility.
  ☆183Updated 9 months ago
• benreynwar / pyvivado
  Python tools for Vivado Projects
  ☆73Updated 5 years ago
• sgherbst / svreal
  Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
  ☆43Updated 3 years ago
• intel / rapid-design-methods-for-developing-hardware-accelerators
  ☆84Updated last year
• unihd-cag / openhmc
  openHMC - an open source Hybrid Memory Cube Controller
  ☆44Updated 8 years ago
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 2 years ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆50Updated 2 years ago
• brianhill11 / FPGA-CNN
  This repo is for ECE44x (Fall2015-Spring2016)
  ☆19Updated 6 years ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆47Updated this week
• cfelton / rhea
  A collection of MyHDL cores and tools for complex digital circuit design
  ☆85Updated 5 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆64Updated 2 months ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆63Updated 4 months ago
• mbgh / aes128-hdl
  A high-throughput VHDL and SystemVerilog implementation of AES-128 including scripts for a full front-end design process.
  ☆38Updated 10 years ago
• devbisme / myhdl-resources
  A collection of awesome MyHDL tutorials, projects and third-party tools.
  ☆93Updated 3 years ago
• shaneleonard / neural-hardware
  Verilog library for implementing neural networks.
  ☆24Updated 10 years ago
• Xilinx / SDSoC_Examples
  ☆82Updated 4 years ago
• hukenovs / fp23fftk
  Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).
  ☆55Updated 2 years ago
• awai54st / LUTNet
  ☆55Updated 4 years ago
• SymbiFlow / vtr-verilog-to-routing
  SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆37Updated 3 months ago
• FPHDL / fphdl
  VHDL-2008 Support Library
  ☆56Updated 8 years ago
• Xilinx / RFNoC-HLS-NeuralNet
  ☆104Updated 5 years ago
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆84Updated 5 years ago
• spcl / apfp
  FPGA acceleration of arbitrary precision floating point computations.
  ☆37Updated 2 years ago
• cornell-brg / pymtl-tut-hls
  Tutorial for integrating PyMTL and Vivado HLS
  ☆17Updated 8 years ago
• PeterOgden / overlay_tutorial
  Premade bitstreams and block designs to complemented the PYNQ overlay tutorial
  ☆39Updated 2 years ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆169Updated 10 months ago
• DreamIP / haddoc2
  Caffe to VHDL
  ☆66Updated 4 years ago