Alternatives and similar repositories for fxpmath:

Users that are interested in fxpmath are comparing it to the libraries listed below

• Xilinx / finn-examples
  Dataflow QNN inference accelerator examples on FPGAs
  ☆196Updated this week
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆240Updated last week
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆157Updated 2 months ago
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆188Updated last month
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆266Updated 2 months ago
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆69Updated last month
• ZZZZzzzzac / numfi
  a subclass of numpy.ndarray that does fixed-point arithmetic
  ☆12Updated 5 months ago
• phanrahan / magma
  magma circuits
  ☆255Updated 3 months ago
• esl-epfl / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆154Updated this week
• sscs-ose / sscs-ose-code-a-chip.github.io
  IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)
  ☆164Updated 3 weeks ago
• MakarenaLabs / Common-PL-Devices-on-PYNQ
  Integration on PL side of Zynq7000 for PYNQ framework of common industrial devices (GPIO, I2C, SPI and UART)
  ☆32Updated 3 years ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆264Updated last week
• kevinpt / symbolator
  HDL symbol generator
  ☆186Updated last year
• definelicht / hlslib
  A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
  ☆311Updated 8 months ago
• spcl / gemm_hls
  Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
  ☆316Updated 2 years ago
• themperek / cocotb-test
  Unit testing for cocotb
  ☆153Updated 2 weeks ago
• drichmond / RISC-V-On-PYNQ
  RISC-V Integration for PYNQ
  ☆167Updated 5 years ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆108Updated this week
• fastmachinelearning / hls4ml-tutorial
  Tutorial notebooks for hls4ml
  ☆313Updated last week
• jeremiah-c-leary / vhdl-style-guide
  Style guide enforcement for VHDL
  ☆195Updated this week
• Xilinx / XilinxBoardStore
  ☆272Updated last month
• pymtl / pymtl3
  Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
  ☆396Updated last month
• raysalemi / Python4RTLVerification
  ☆130Updated 2 years ago
• Xilinx / Vivado-Design-Tutorials
  ☆173Updated this week
• xupgit / Advanced-Embedded-System-Design-Flow-on-Zynq
  ☆52Updated 5 years ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆131Updated this week
• dpretet / svut
  SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
  ☆72Updated 2 months ago
• Xilinx / DPU-PYNQ
  DPU on PYNQ
  ☆208Updated 11 months ago
• Fraunhofer-IMS / airisc_core_complex
  Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
  ☆83Updated last year
• ehw-fit / evoapproxlib
  Library of approximate arithmetic circuits
  ☆53Updated 2 years ago