francof2a / fxpmathLinks
A python library for fractional fixed-point (base 2) arithmetic and binary manipulation with Numpy compatibility.
☆202Updated last year
Alternatives and similar repositories for fxpmath
Users that are interested in fxpmath are comparing it to the libraries listed below
Sorting:
- Style guide enforcement for VHDL☆232Updated 2 weeks ago
- A Python package to use FPGA development tools programmatically.☆143Updated 10 months ago
- Fixed Point Math Library for Verilog☆145Updated 11 years ago
- magma circuits☆264Updated last year
- APyTypes - Algorithmic data types for Python☆39Updated this week
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆444Updated 5 months ago
- ☆312Updated last week
- Integration on PL side of Zynq7000 for PYNQ framework of common industrial devices (GPIO, I2C, SPI and UART)☆38Updated 4 years ago
- Unit testing for cocotb☆166Updated last month
- Fixed point package for Python.☆36Updated 2 years ago
- FPGA and Digital ASIC Build System☆81Updated 3 weeks ago
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆196Updated this week
- Control and Status Register map generator for HDL projects☆129Updated 8 months ago
- Tutorial notebooks for hls4ml☆402Updated last week
- A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Si…☆293Updated 2 months ago
- A collection of demonstration digital filters☆165Updated 2 years ago
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆200Updated 3 weeks ago
- Dataflow QNN inference accelerator examples on FPGAs☆241Updated 5 months ago
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆334Updated last year
- RISC-V Integration for PYNQ☆180Updated 6 years ago
- VHDL-2008 Support Library☆58Updated 9 years ago
- ☆248Updated this week
- Fixed point arithmetic python package☆38Updated 2 years ago
- Python wrapper for verilator model☆92Updated last year
- Train and deploy LUT-based neural networks on FPGAs☆106Updated last year
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆221Updated last month
- Avnet Board Definition Files☆140Updated 2 weeks ago
- Verilog digital signal processing components☆169Updated 3 years ago
- ☆104Updated 2 years ago
- SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!☆79Updated last year