A python library for fractional fixed-point (base 2) arithmetic and binary manipulation with Numpy compatibility.
☆204Feb 12, 2024Updated 2 years ago
Alternatives and similar repositories for fxpmath
Users that are interested in fxpmath are comparing it to the libraries listed below
Sorting:
- Fixed point package for Python.☆36Apr 28, 2023Updated 2 years ago
- Interfacing VHDL and foreign languages with VUnit☆15Feb 20, 2020Updated 6 years ago
- ☆35Sep 12, 2019Updated 6 years ago
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Jan 13, 2022Updated 4 years ago
- ☆33Apr 30, 2023Updated 2 years ago
- VHDL String Formatting Library☆27Apr 27, 2024Updated last year
- cryptography ip-cores in vhdl / verilog☆41Feb 20, 2021Updated 5 years ago
- Example of Test Driven Design with VUnit☆16Nov 22, 2021Updated 4 years ago
- VUnit is a unit testing framework for VHDL/SystemVerilog☆818Feb 26, 2026Updated last week
- cocotb: Python-based chip (RTL) verification☆2,266Updated this week
- Classify modulation of signals☆16Jan 16, 2020Updated 6 years ago
- SpinalHDL Hardware Math Library☆96Jul 12, 2024Updated last year
- A flexible and scalable development platform for modern FPGA projects.☆41Feb 2, 2026Updated last month
- A huge VHDL library for FPGA and digital ASIC development☆449Feb 23, 2026Updated last week
- An abstraction library for interfacing EDA tools☆756Feb 18, 2026Updated 2 weeks ago
- Cross EDA Abstraction and Automation☆41Nov 17, 2025Updated 3 months ago
- Style guide enforcement for VHDL☆234Feb 5, 2026Updated last month
- Fixed point arithmetic python package☆38Dec 31, 2023Updated 2 years ago
- USB -> AXI Debug Bridge☆42Jun 5, 2021Updated 4 years ago
- Hardware generator debugger☆77Feb 12, 2024Updated 2 years ago
- openEMS High-level layer☆19Mar 6, 2025Updated last year
- A translation of the Xilinx XPM library to VHDL for simulation purposes☆64Nov 7, 2025Updated 4 months ago
- ☆21Mar 9, 2021Updated 4 years ago
- SAMO: Streaming Architecture Mapping Optimisation☆34Oct 4, 2023Updated 2 years ago
- ☆19Dec 18, 2024Updated last year
- A Vivado HLS Command Line Helper Tool☆36Oct 6, 2021Updated 4 years ago
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Jul 7, 2022Updated 3 years ago
- Low Precision Arithmetic Simulation in PyTorch☆292May 20, 2024Updated last year
- CES VHDL utility library, with packages, memories, FIFOs, Clock Domain Crossing and more useful VHDL modules☆11Jan 17, 2022Updated 4 years ago
- A curated list of awesome resources for HDL design and verification☆169Feb 27, 2026Updated last week
- WAL enables programmable waveform analysis.☆164Nov 10, 2025Updated 3 months ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,391Feb 13, 2026Updated 3 weeks ago
- SGen is a generator capable of producing efficient hardware designs operating on streaming datasets. “Streaming” means that the dataset i…☆25Nov 11, 2025Updated 3 months ago
- Python Filter Design Analysis Tool☆728Feb 2, 2026Updated last month
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆699Dec 14, 2025Updated 2 months ago
- Fixed-point math library with VHDL, Python and MATLAB support☆37Oct 15, 2025Updated 4 months ago
- GHDL C extensions☆11Feb 20, 2020Updated 6 years ago
- Standard and Curated cores, tested and working.☆11Dec 29, 2022Updated 3 years ago
- IPv4/UDP stack written in VHDL code, for interfacing with an FPGA over Ethernet☆11Jun 2, 2021Updated 4 years ago