francof2a / fxpmath
A python library for fractional fixed-point (base 2) arithmetic and binary manipulation with Numpy compatibility.
☆179Updated 7 months ago
Related projects: ⓘ
- a subclass of numpy.ndarray that does fixed-point arithmetic☆12Updated last month
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆253Updated last week
- Fixed point package for Python.☆34Updated last year
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆140Updated 3 weeks ago
- magma circuits☆242Updated 3 months ago
- Fast inference of Boosted Decision Trees in FPGAs☆47Updated 2 weeks ago
- Dataflow QNN inference accelerator examples on FPGAs☆174Updated last month
- Vitis HLS Library for FINN☆173Updated 3 months ago
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆328Updated this week
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆253Updated this week
- ☆102Updated 5 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆58Updated last month
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆140Updated this week
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆298Updated 2 years ago
- Unit testing for cocotb☆144Updated last month
- Package for performing fixed-point, arbitrary-precision arithmetic in Python.☆64Updated 6 months ago
- ☆248Updated last month
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆92Updated this week
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆297Updated 4 months ago
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆369Updated last month
- ☆81Updated 3 months ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆223Updated last month
- FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)☆259Updated 4 years ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆199Updated 3 months ago
- RISC-V Integration for PYNQ☆165Updated 5 years ago
- Fixed Point Math Library for Verilog☆117Updated 10 years ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆191Updated last month
- Style guide enforcement for VHDL☆185Updated last week
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆188Updated 2 years ago
- ☆53Updated 4 years ago