francof2a / fxpmathLinks
A python library for fractional fixed-point (base 2) arithmetic and binary manipulation with Numpy compatibility.
☆194Updated last year
Alternatives and similar repositories for fxpmath
Users that are interested in fxpmath are comparing it to the libraries listed below
Sorting:
- A Python package to use FPGA development tools programmatically.☆138Updated 3 months ago
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆419Updated 2 months ago
- Style guide enforcement for VHDL☆211Updated last week
- Unit testing for cocotb☆160Updated last month
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆186Updated 2 months ago
- Integration on PL side of Zynq7000 for PYNQ framework of common industrial devices (GPIO, I2C, SPI and UART)☆38Updated 4 years ago
- FPGA and Digital ASIC Build System☆74Updated this week
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆172Updated this week
- ☆291Updated this week
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆213Updated this week
- Vitis Model Composer Examples and Tutorials☆102Updated last month
- A huge VHDL library for FPGA and digital ASIC development☆391Updated this week
- magma circuits☆261Updated 8 months ago
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆321Updated 5 months ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆284Updated 2 months ago
- Tutorial notebooks for hls4ml☆348Updated 3 weeks ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆257Updated this week
- Fully Open Source FASOC generators built on top of open-source EDA tools☆283Updated 2 weeks ago
- Fabric generator and CAD tools.☆190Updated last week
- Python wrapper for verilator model☆86Updated last year
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆275Updated 2 months ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆85Updated last month
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆221Updated 3 weeks ago
- Board files to build Ultra 96 PYNQ image☆155Updated 7 months ago
- VHDL-2008 Support Library☆57Updated 8 years ago
- HW Design: A Functional Approach☆146Updated 2 years ago
- RISC-V Integration for PYNQ☆174Updated 6 years ago
- A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Si…☆282Updated last week
- SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!☆80Updated 8 months ago
- ☆213Updated last month