SEL-FOSS / fixedpointLinks
Fixed point arithmetic python package
☆37Updated last year
Alternatives and similar repositories for fixedpoint
Users that are interested in fixedpoint are comparing it to the libraries listed below
Sorting:
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆68Updated 9 months ago
- Streaming based VHDL parser.☆84Updated 10 months ago
- Python script to transform a VCD file to wavedrom format☆77Updated 2 years ago
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆48Updated this week
- A tool for merging the MyHDL workflow with Vivado☆20Updated 5 years ago
- ☆26Updated last year
- Python tools for Vivado Projects☆73Updated 6 years ago
- Extensible FPGA control platform☆62Updated 2 years ago
- FPGA and Digital ASIC Build System☆74Updated 2 weeks ago
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆40Updated 6 years ago
- Running Python code in SystemVerilog☆69Updated this week
- An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…☆28Updated 4 months ago
- Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.☆58Updated 6 months ago
- Vivado build system☆69Updated 5 months ago
- Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.☆61Updated last week
- SpinalHDL Hardware Math Library☆86Updated 10 months ago
- A Vivado HLS Command Line Helper Tool☆36Updated 3 years ago
- ☆38Updated last year
- Framework Open EDA Gui☆65Updated 5 months ago
- hardware library for hwt (= ipcore repo)☆37Updated last week
- Pre-packaged testbenching tools and reusable bus interfaces for cocotb☆65Updated 7 months ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆33Updated 3 months ago
- An open-source HDL register code generator fast enough to run in real time.☆68Updated this week
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆55Updated this week
- Fork of OpenCores jpegencode with Cocotb testbench☆44Updated 9 years ago
- Example of Test Driven Design with VUnit☆14Updated 3 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆60Updated this week
- IP-core package generator for AXI4/Avalon☆22Updated 6 years ago
- Doxygen with verilog support☆37Updated 6 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆26Updated last year