Alternatives and similar repositories for fixedpoint

Users that are interested in fixedpoint are comparing it to the libraries listed below

• benreynwar / pyvivado
  Python tools for Vivado Projects
  ☆72Updated 6 years ago
• FPHDL / fphdl
  VHDL-2008 Support Library
  ☆57Updated 9 years ago
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆78Updated 2 weeks ago
• suoto / fpga_cores
  ☆33Updated 2 years ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆62Updated 3 weeks ago
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆69Updated 10 months ago
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆84Updated last year
• SanDisk-Open-Source / pyvcd
  Python package for writing Value Change Dump (VCD) files.
  ☆126Updated 11 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆76Updated 3 months ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆81Updated 3 years ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆41Updated 7 years ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆35Updated 7 years ago
• cirosantilli / vcdvcd
  Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
  ☆63Updated last week
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆38Updated 6 years ago
• accellera-official / PySysC
  Public repository for PySysC, (From SC Common Practices Subgroup)
  ☆53Updated last year
• PyFPGA / pyfpga
  A Python package to use FPGA development tools programmatically.
  ☆140Updated 7 months ago
• sgherbst / svreal
  Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
  ☆48Updated 4 years ago
• dpretet / svut
  SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
  ☆79Updated last year
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆57Updated last month
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• Digilent / digilent-vivado-scripts
  ☆69Updated 3 months ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆50Updated last year
• benjmarshall / hlsclt
  A Vivado HLS Command Line Helper Tool
  ☆36Updated 4 years ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆70Updated 4 months ago
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆66Updated 2 weeks ago
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆218Updated last week
• hlslibs / ac_math
  Algorithmic C Math Library
  ☆65Updated 5 months ago
• antmicro / cocotb-verilator-build
  ☆26Updated 2 years ago
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆68Updated 3 weeks ago
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆72Updated last year