ASCII art figures can be parsed and output as SVG, PNG, JPEG, PDF and more. This project provides a python package and a command line script.
☆21Jul 5, 2017Updated 8 years ago
Alternatives and similar repositories for aafigure
Users that are interested in aafigure are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Jan 13, 2022Updated 4 years ago
- A first approach of getting a pure Ada program running on an FPGA with SaxonSOC☆10Apr 12, 2021Updated 5 years ago
- Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.☆14Sep 22, 2025Updated 8 months ago
- VHDL related news.☆27Updated this week
- GitHub-based statistics highlighting interesting facts about the HDL industry☆12Jul 6, 2023Updated 2 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Example of Test Driven Design with VUnit☆16Nov 22, 2021Updated 4 years ago
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.☆14Feb 24, 2026Updated 3 months ago
- GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.☆16Apr 10, 2025Updated last year
- Generator for VHDL regular expression matchers☆15Jan 11, 2021Updated 5 years ago
- A getting started presentation (with examples) about how to use FLOSS for FPGA development.☆36Sep 18, 2023Updated 2 years ago
- VHDLproc is a VHDL preprocessor☆24May 12, 2022Updated 4 years ago
- VHDL dependency analyzer☆25Mar 10, 2020Updated 6 years ago
- Drop In USB CDC ACM core for iCE40 FPGA☆36Sep 5, 2021Updated 4 years ago
- PNG encoder, implemented in VHDL☆23Mar 30, 2024Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆34Mar 7, 2026Updated 3 months ago
- ☆33Jun 2, 2026Updated last week
- Virtual development board for HDL design☆42Mar 31, 2023Updated 3 years ago
- Fixed point package for Python.☆37Apr 28, 2023Updated 3 years ago
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆32Jan 30, 2025Updated last year
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆48Feb 12, 2026Updated 3 months ago
- cryptography ip-cores in vhdl / verilog☆42Feb 20, 2021Updated 5 years ago
- ❓ keep track of who has which FlexLM licenses checked out☆15Jan 24, 2012Updated 14 years ago
- Rust proof-of-concept for GPU waveform rendering☆13Jul 22, 2020Updated 5 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- ☆26Apr 3, 2023Updated 3 years ago
- ulx3s ghdl examples☆15Mar 6, 2021Updated 5 years ago
- Create Wheel from CMake projects☆27Jun 3, 2026Updated last week
- Experiments with Cologne Chip's GateMate FPGA architecture☆19Nov 16, 2023Updated 2 years ago
- ☆16Sep 29, 2022Updated 3 years ago
- Building and deploying container images for open source electronic design automation (EDA)☆122Oct 3, 2024Updated last year
- Specification of the Wishbone SoC Interconnect Architecture☆54Jun 5, 2022Updated 4 years ago
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- Ada-language framework☆52Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Episode I - RISCV CPU implementation tutorial for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga☆17Apr 7, 2026Updated 2 months ago
- Logistic regression FPGA core☆19Apr 7, 2021Updated 5 years ago
- ☆16Apr 8, 2024Updated 2 years ago
- Converts the help message of a program into a manpage☆27May 4, 2021Updated 5 years ago
- A simple asyncio friendly replacement for multiprocessing to run coroutines in a separate process.☆14Sep 10, 2020Updated 5 years ago
- Tiny TeX distribution built on Web2C and LuaTeX.☆10Oct 2, 2025Updated 8 months ago
- This repository is an excuse to learn about Convolutional Neural Networks by implementing one in FPGA. The main goal is to learn, and to …☆12Jul 12, 2020Updated 5 years ago