sifive / wake
The SiFive wake build tool
☆87Updated this week
Alternatives and similar repositories for wake:
Users that are interested in wake are comparing it to the libraries listed below
- Tile based architecture designed for computing efficiency, scalability and generality☆240Updated 3 weeks ago
- Chisel/Firrtl execution engine☆153Updated 4 months ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆138Updated last month
- Library to compile Chisel circuits using LLVM/MLIR (CIRCT)☆70Updated last year
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆163Updated 5 months ago
- Time-sensitive affine types for predictable hardware generation☆138Updated 6 months ago
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆219Updated last year
- Main page☆125Updated 4 years ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆146Updated 2 years ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆220Updated last month
- ☆151Updated 10 months ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆154Updated this week
- ☆82Updated last week
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆98Updated 5 years ago
- (System)Verilog to Chisel translator☆109Updated 2 years ago
- The specification for the FIRRTL language☆49Updated last week
- RISC-V Formal Verification Framework☆120Updated 3 months ago
- 👾 Design ∪ Hardware☆72Updated 2 months ago
- Working Draft of the RISC-V J Extension Specification☆173Updated 2 weeks ago
- A core language for rule-based hardware design 🦑☆146Updated 3 months ago
- high-performance RTL simulator☆149Updated 6 months ago
- RISC-V Torture Test☆175Updated 6 months ago
- Hardware generator debugger☆73Updated 11 months ago
- Provides dot visualizations of chisel/firrtl circuits☆119Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 8 months ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 5 years ago
- A tiny POWER Open ISA soft processor written in Chisel☆106Updated last year
- Working draft of the proposed RISC-V Bitmanipulation extension☆207Updated 9 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆138Updated 2 months ago