Control and Status Register map generator for HDL projects
☆145May 24, 2025Updated last year
Alternatives and similar repositories for corsair
Users that are interested in corsair are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 🇯 JSON encoder and decoder in pure SystemVerilog☆16Jul 7, 2024Updated 2 years ago
- Contains source code for sin/cos table verification using UVM☆23Mar 9, 2021Updated 5 years ago
- Code generation tool for control and status registers☆464Jul 16, 2026Updated 3 weeks ago
- Control and status register code generator toolchain☆208Jul 14, 2026Updated 3 weeks ago
- ☆20Jul 28, 2026Updated 2 weeks ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Example of Python and PyTest powered workflow for a HDL simulation☆15Jan 17, 2021Updated 5 years ago
- Verilog (SystemVerilog) coding style☆42Jan 7, 2019Updated 7 years ago
- Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.☆28Jul 31, 2023Updated 3 years ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆208Jun 3, 2026Updated 2 months ago
- An abstraction library for interfacing EDA tools☆786Updated this week
- Resources for my first book☆23Jun 21, 2023Updated 3 years ago
- WaveDrom compatible python command line☆118Jun 2, 2023Updated 3 years ago
- Drawio => VHDL and Verilog☆62Oct 15, 2023Updated 2 years ago
- Basic Common Modules☆48Jul 16, 2026Updated 3 weeks ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-sla…☆27Mar 5, 2025Updated last year
- A Python package for generating HDL wrappers and top modules for HDL sources☆132Updated this week
- Use ECP5 JTAG port to interact with user design☆33Jul 23, 2021Updated 5 years ago
- Xilinx AXI VIP example of use☆45Apr 24, 2021Updated 5 years ago
- VUnit is a unit testing framework for VHDL/SystemVerilog☆843Updated this week
- Style guide enforcement for VHDL☆249Jul 24, 2026Updated 2 weeks ago
- SystemRDL 2.0 language compiler front-end☆282Apr 10, 2026Updated 4 months ago
- Репозиторий факультатива по функциональной верификации НИУ МИЭТ☆19Aug 24, 2024Updated last year
- 📊 Tools collection (NumPy + Matplotlib based) to do spectral analysis and calculate the key performance parameters of an ADC☆22Jun 26, 2023Updated 3 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- An open-source HDL register code generator fast enough to run in real time.☆91Updated this week
- Dockerfile for ModelSim Version 16 GUI☆15Aug 16, 2021Updated 4 years ago
- Coverview☆33Updated this week
- A dependency management tool for hardware projects.☆383Updated this week
- Simple Python Module to access PCIe Endpoint BARs☆23Dec 15, 2025Updated 7 months ago
- Python package for writing Value Change Dump (VCD) files.☆135Updated this week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,447Updated this week
- Constrained random stimuli generation for C++ and SystemC☆53Nov 29, 2023Updated 2 years ago
- Simple pin assignment generator for IC case☆19Feb 14, 2017Updated 9 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Verilog AXI stream components for FPGA implementation☆911Feb 27, 2025Updated last year
- ☆32Jun 16, 2024Updated 2 years ago
- Mastering FPGASIC Book☆19Oct 26, 2025Updated 9 months ago
- cocotb: Python-based chip (RTL) verification☆2,471Updated this week
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆18Aug 1, 2019Updated 7 years ago
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆736Updated this week
- Testing FPGA2SDRAM interface on Altera Cyclone V SoC☆14May 12, 2015Updated 11 years ago