Control and Status Register map generator for HDL projects
☆144May 24, 2025Updated last year
Alternatives and similar repositories for corsair
Users that are interested in corsair are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 🇯 JSON encoder and decoder in pure SystemVerilog☆16Jul 7, 2024Updated 2 years ago
- Contains source code for sin/cos table verification using UVM☆23Mar 9, 2021Updated 5 years ago
- Code generation tool for control and status registers☆463Jul 16, 2026Updated last week
- Control and status register code generator toolchain☆201Jul 14, 2026Updated last week
- ☆19Updated this week
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Example of Python and PyTest powered workflow for a HDL simulation☆15Jan 17, 2021Updated 5 years ago
- Verilog (SystemVerilog) coding style☆42Jan 7, 2019Updated 7 years ago
- Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.☆28Jul 31, 2023Updated 2 years ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆208Jun 3, 2026Updated last month
- An abstraction library for interfacing EDA tools☆781Jul 2, 2026Updated 3 weeks ago
- WaveDrom compatible python command line☆117Jun 2, 2023Updated 3 years ago
- Drawio => VHDL and Verilog☆62Oct 15, 2023Updated 2 years ago
- Basic Common Modules☆48Jul 16, 2026Updated last week
- HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-sla…☆27Mar 5, 2025Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- A Python package for generating HDL wrappers and top modules for HDL sources☆128Updated this week
- Use ECP5 JTAG port to interact with user design☆33Jul 23, 2021Updated 5 years ago
- Xilinx AXI VIP example of use☆44Apr 24, 2021Updated 5 years ago
- VUnit is a unit testing framework for VHDL/SystemVerilog☆839May 14, 2026Updated 2 months ago
- Style guide enforcement for VHDL☆247Updated this week
- SystemRDL 2.0 language compiler front-end☆282Apr 10, 2026Updated 3 months ago
- Репозиторий факультатива по функциональной верификации НИУ МИЭТ☆19Aug 24, 2024Updated last year
- 📊 Tools collection (NumPy + Matplotlib based) to do spectral analysis and calculate the key performance parameters of an ADC☆22Jun 26, 2023Updated 3 years ago
- An open-source HDL register code generator fast enough to run in real time.☆91Jul 6, 2026Updated 2 weeks ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Dockerfile for ModelSim Version 16 GUI☆15Aug 16, 2021Updated 4 years ago
- Coverview☆31Updated this week
- A dependency management tool for hardware projects.☆379Updated this week
- Simple Python Module to access PCIe Endpoint BARs☆23Dec 15, 2025Updated 7 months ago
- Python package for writing Value Change Dump (VCD) files.☆135Nov 10, 2024Updated last year
- Package manager and build abstraction tool for FPGA/ASIC development☆1,440Jul 2, 2026Updated 3 weeks ago
- Constrained random stimuli generation for C++ and SystemC☆53Nov 29, 2023Updated 2 years ago
- Simple pin assignment generator for IC case☆19Feb 14, 2017Updated 9 years ago
- Verilog AXI stream components for FPGA implementation☆906Feb 27, 2025Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆32Jun 16, 2024Updated 2 years ago
- Mastering FPGASIC Book☆19Oct 26, 2025Updated 8 months ago
- cocotb: Python-based chip (RTL) verification☆2,451Updated this week
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆18Aug 1, 2019Updated 6 years ago
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆727Dec 14, 2025Updated 7 months ago
- Testing FPGA2SDRAM interface on Altera Cyclone V SoC☆14May 12, 2015Updated 11 years ago
- An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…☆30Jan 13, 2025Updated last year