Control and Status Register map generator for HDL projects
☆133May 24, 2025Updated 9 months ago
Alternatives and similar repositories for corsair
Users that are interested in corsair are comparing it to the libraries listed below
Sorting:
- 🇯 JSON encoder and decoder in pure SystemVerilog☆14Jul 7, 2024Updated last year
- Contains source code for sin/cos table verification using UVM☆21Mar 9, 2021Updated 5 years ago
- ☆18Jan 21, 2026Updated 2 months ago
- Code generation tool for control and status registers☆450Mar 14, 2026Updated last week
- Control and status register code generator toolchain☆179Feb 27, 2026Updated 3 weeks ago
- Example of Python and PyTest powered workflow for a HDL simulation☆15Jan 17, 2021Updated 5 years ago
- Resources for my first book☆23Jun 21, 2023Updated 2 years ago
- Репозиторий факультатива по функциональной верификации НИУ МИЭТ☆16Aug 24, 2024Updated last year
- Verilog (SystemVerilog) coding style☆42Jan 7, 2019Updated 7 years ago
- An abstraction library for interfacing EDA tools☆754Mar 11, 2026Updated last week
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆207Oct 21, 2024Updated last year
- Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.☆26Jul 31, 2023Updated 2 years ago
- ☆40Mar 9, 2026Updated last week
- WaveDrom compatible python command line☆114Jun 2, 2023Updated 2 years ago
- HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-sla…☆26Mar 5, 2025Updated last year
- Basic Common Modules☆46Mar 11, 2026Updated last week
- Drawio => VHDL and Verilog☆61Oct 15, 2023Updated 2 years ago
- An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…☆30Jan 13, 2025Updated last year
- Use ECP5 JTAG port to interact with user design☆33Jul 23, 2021Updated 4 years ago
- Dockerfile for ModelSim Version 16 GUI☆15Aug 16, 2021Updated 4 years ago
- Xilinx AXI VIP example of use☆43Apr 24, 2021Updated 4 years ago
- VUnit is a unit testing framework for VHDL/SystemVerilog☆820Mar 12, 2026Updated last week
- Verilog VPI module to dump FST (Fast Signal Trace) databases☆20Sep 19, 2023Updated 2 years ago
- A dependency management tool for hardware projects.☆354Mar 12, 2026Updated last week
- SystemRDL 2.0 language compiler front-end☆275Mar 8, 2026Updated last week
- Style guide enforcement for VHDL☆235Feb 5, 2026Updated last month
- 📊 Tools collection (NumPy + Matplotlib based) to do spectral analysis and calculate the key performance parameters of an ADC☆22Jun 26, 2023Updated 2 years ago
- Simple Python Module to access PCIe Endpoint BARs☆23Dec 15, 2025Updated 3 months ago
- Python package for writing Value Change Dump (VCD) files.☆131Nov 10, 2024Updated last year
- Constrained random stimuli generation for C++ and SystemC☆53Nov 29, 2023Updated 2 years ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,396Feb 13, 2026Updated last month
- Simple pin assignment generator for IC case☆19Feb 14, 2017Updated 9 years ago
- Verilog AXI stream components for FPGA implementation☆870Feb 27, 2025Updated last year
- Mastering FPGASIC Book☆18Oct 26, 2025Updated 4 months ago
- ☆30Jun 16, 2024Updated last year
- cocotb: Python-based chip (RTL) verification☆2,284Mar 13, 2026Updated last week
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆76Dec 12, 2025Updated 3 months ago
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆702Dec 14, 2025Updated 3 months ago
- The UVM written in Python☆510Mar 9, 2026Updated last week