Alternatives and similar repositories for corsair

Users that are interested in corsair are comparing it to the libraries listed below

• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆137Updated last week
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆168Updated last week
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆105Updated 3 years ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆64Updated 2 weeks ago
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆65Updated 7 months ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆43Updated 4 months ago
• raysalemi / Python4RTLVerification
  ☆159Updated 2 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆139Updated 2 years ago
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆92Updated 4 years ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆147Updated 3 months ago
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆113Updated last year
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆135Updated this week
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆77Updated 2 years ago
• thomasrussellmurphy / stx_cookbook
  Altera Advanced Synthesis Cookbook 11.0
  ☆104Updated 2 years ago
• olofk / ipyxact
  Python-based IP-XACT parser
  ☆132Updated 11 months ago
• MahmouodMagdi / Clock-Domain-Crossing-Synchronizers
  Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…
  ☆59Updated last year
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆68Updated this week
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆121Updated this week
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 4 months ago
• SparcLab / OpenSERDES
  Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
  ☆162Updated 3 years ago
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆71Updated 10 months ago
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆34Updated last year
• themperek / cocotb-test
  Unit testing for cocotb
  ☆160Updated 3 weeks ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆166Updated 6 months ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆115Updated last year
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆61Updated 3 years ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆52Updated last year
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆262Updated last year
• hypernyan / eth_vlg
  ☆70Updated 3 years ago
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆69Updated 5 months ago