Alternatives and similar repositories for activecore

Users that are interested in activecore are comparing it to the libraries listed below

• chipsalliance / uvm-verilator
  ☆97Updated last year
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆29Updated 2 years ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆153Updated this week
• aignacio / nox
  RISC-V Nox core
  ☆68Updated last month
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆36Updated last month
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆209Updated 5 months ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆41Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆120Updated last month
• spider-tronix / Standard-Cell-Characterization
  Open Source tool to build liberty files and for Characterizing Standard Cells.
  ☆27Updated 4 years ago
• maltanar / axi-in-chisel
  Examples for creating AXI-interfaced peripherals in Chisel
  ☆76Updated 9 years ago
• Lampro-Mellon / LM-RISCV-DV
  An Open-Source Design and Verification Environment for RISC-V
  ☆83Updated 4 years ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆101Updated 2 months ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆54Updated 5 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆139Updated last month
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆107Updated 4 years ago
• pulp-platform / svase
  ☆32Updated 7 months ago
• verilator / example-systemverilog
  ☆40Updated last year
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆116Updated 3 years ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆89Updated last week
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated 2 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆75Updated last month
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆37Updated 2 years ago
• pulp-platform / clint
  RISC-V Core Local Interrupt Controller (CLINT)
  ☆28Updated 2 months ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆59Updated 10 months ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆131Updated last week
• ben-marshall / verilog-vcd-parser
  A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
  ☆98Updated 3 years ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆117Updated last year
• mciepluc / apbi2c_cocotb_example
  An example Python-based MDV testbench for apbi2c core
  ☆30Updated last year
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆78Updated 3 years ago