AntonovAlexander / activecore
Hardware generation library based on "Kernel IP" (KIP) cores: programmable execution kernels inferred from microarchitectural templates
☆28Updated 2 months ago
Alternatives and similar repositories for activecore:
Users that are interested in activecore are comparing it to the libraries listed below
- Making cocotb testbenches that bit easier☆26Updated 3 weeks ago
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆21Updated 2 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- SystemVerilog frontend for Yosys☆69Updated last week
- Static Timing Analysis Full Course☆47Updated 2 years ago
- SystemVerilog Linter based on pyslang☆25Updated 3 weeks ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆65Updated 4 months ago
- ☆23Updated 4 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆46Updated this week
- Repository gathering basic modules for CDC purpose☆51Updated 5 years ago
- Open source RTL simulation acceleration on commodity hardware☆23Updated last year
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆61Updated last month
- YosysHQ SVA AXI Properties☆37Updated last year
- Xilinx AXI VIP example of use☆33Updated 3 years ago
- ☆31Updated 3 weeks ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆32Updated 4 years ago
- Platform Level Interrupt Controller☆35Updated 8 months ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆41Updated 3 years ago
- An automatic clock gating utility☆43Updated 6 months ago
- This is full tutorial of UVM (Universal Verification Methodology) for a simple ALU unit☆21Updated 6 years ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆24Updated 3 years ago
- Open source ISS and logic RISC-V 32 bit project☆41Updated 2 months ago
- SystemVerilog language-oriented exercises☆58Updated last week
- A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.☆91Updated 2 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆34Updated 2 years ago
- Python script to transform a VCD file to wavedrom format☆75Updated 2 years ago
- Contains source code for sin/cos table verification using UVM☆20Updated 3 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 8 months ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆79Updated 3 months ago