semisgdh / SGDH-RVSoCLinks
An incredibly small 32-bit RISC-V rv32acim CPU capable of running Linux on FPGA, and software simulations.
☆26Updated 11 months ago
Alternatives and similar repositories for SGDH-RVSoC
Users that are interested in SGDH-RVSoC are comparing it to the libraries listed below
Sorting:
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆155Updated 8 months ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆81Updated 2 years ago
- AMD University Program HLS tutorial☆118Updated last year
- Squeezenet V1.1 on Cyclone V SoC-FPGA at 450ms/image, 20x faster than ARM A9 processor alone. A project for 2017 Innovate FPGA design con…☆112Updated 7 years ago
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆316Updated last month
- Vitis HLS Library for FINN☆209Updated last month
- ☆221Updated last year
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆105Updated 5 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆66Updated 5 years ago
- DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator☆418Updated last year
- An AXI4 crossbar implementation in SystemVerilog☆178Updated 2 months ago
- A Chisel RTL generator for network-on-chip interconnects☆217Updated 2 months ago
- RISC-V SystemC-TLM simulator☆329Updated this week
- IEEE 754 floating point unit in Verilog☆148Updated 9 years ago
- Processing-In-Memory (PIM) Simulator☆198Updated 10 months ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆116Updated 3 months ago
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆203Updated 3 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆202Updated 5 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆174Updated 5 years ago
- Small-scale Tensor Processing Unit built on an FPGA☆207Updated 6 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆96Updated last week
- OpenCL HLS based CNN Accelerator on Intel DE10 Nano FPGA.☆80Updated 2 years ago
- A matrix extension proposal for AI applications under RISC-V architecture☆155Updated 8 months ago
- ai_accelerator_basic_for_student (no solve)☆13Updated 5 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆133Updated 7 years ago
- A Fast, Low-Overhead On-chip Network☆232Updated last week
- ☆14Updated 2 years ago
- Verilog implementation of Softmax function☆74Updated 3 years ago
- GPGPU supporting RISCV-V, developed with verilog HDL☆121Updated 8 months ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆94Updated 6 years ago