Alternatives and similar repositories for SGDH-RVSoC

Users that are interested in SGDH-RVSoC are comparing it to the libraries listed below

• gju06051 / TPU_HW_Verilog
  ☆14Updated 2 years ago
• BoooC / CNN-Accelerator-Based-on-Eyeriss-v2
  A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
  ☆66Updated 2 months ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆100Updated 4 years ago
• hyoukjun / DesignCNNAccelerators
  Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017
  ☆29Updated 6 years ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆74Updated last year
• SAITPublic / PIMSimulator
  Processing-In-Memory (PIM) Simulator
  ☆161Updated 5 months ago
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆74Updated 10 years ago
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆62Updated 5 years ago
• thousrm / universal_NPU-CNN_accelerator
  hardware design of universal NPU(CNN accelerator) for various convolution neural network
  ☆119Updated 2 months ago
• matbi86 / 01_ai_accelerator_basic_for_student
  ai_accelerator_basic_for_student (no solve)
  ☆11Updated 5 years ago
• dldldlfma / eyeriss_v1
  ☆12Updated 5 years ago
• agalimberti / NoCRouter
  RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
  ☆126Updated 7 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆147Updated last week
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆158Updated 5 years ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆73Updated 7 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆56Updated last month
• Xilinx / xup_high_level_synthesis_design_flow
  AMD University Program HLS tutorial
  ☆92Updated 6 months ago
• suhasr1991 / Convolutional-Neural-Network-hardware-using-Verilog
  A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…
  ☆18Updated 7 years ago
• Parimala6 / Floating-point-MAC-verilog
  32 - bit floating point Multiplier Accumulator Unit (MAC)
  ☆30Updated 4 years ago
• abdelazeem201 / ICC2_scripts
  This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.
  ☆17Updated last year
• xupgit / Zynq-Design-using-Vivado
  This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.
  ☆84Updated last year
• kuladeepsaireddy / OpenNoc
  ☆33Updated 6 years ago
• akilm / FPU-IEEE-754
  Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…
  ☆53Updated 9 months ago
• THU-DSP-LAB / ventus-gpgpu-verilog
  GPGPU supporting RISCV-V, developed with verilog HDL
  ☆98Updated 2 months ago
• BUAA-CI-LAB / Literatures-on-SRAM-based-CIM
  A reading list for SRAM-based Compute-In-Memory (CIM) research.
  ☆61Updated 3 months ago
• hyoukjun / OpenSMART
  Public release
  ☆51Updated 5 years ago
• neasotho / SystolicArray_FPGA
  Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board
  ☆14Updated 4 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆74Updated 7 years ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆174Updated 2 years ago
• black-parrot-hdk / zynq-parrot
  BlackParrot on Zynq
  ☆41Updated 2 months ago