Alternatives and similar repositories for SGDH-RVSoC

Users that are interested in SGDH-RVSoC are comparing it to the libraries listed below

• thousrm / universal_NPU-CNN_accelerator
  hardware design of universal NPU(CNN accelerator) for various convolution neural network
  ☆148Updated 6 months ago
• Xilinx / xup_high_level_synthesis_design_flow
  AMD University Program HLS tutorial
  ☆108Updated 10 months ago
• tukl-msd / DRAMSys
  DRAMSys a SystemC TLM-2.0 based DRAM simulator.
  ☆304Updated 4 months ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆210Updated last month
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆80Updated 2 years ago
• SAITPublic / PIMSimulator
  Processing-In-Memory (PIM) Simulator
  ☆193Updated 9 months ago
• umd-memsys / DRAMsim3
  DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator
  ☆409Updated last year
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆104Updated 4 years ago
• BoooC / CNN-Accelerator-Based-on-Eyeriss-v2
  A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
  ☆108Updated 2 months ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆175Updated 3 weeks ago
• cameronshinn / tiny-tpu
  Small-scale Tensor Processing Unit built on an FPGA
  ☆202Updated 6 years ago
• abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU
  IC implementation of Systolic Array for TPU
  ☆278Updated 11 months ago
• Er1cZ / Deploying_CNN_on_FPGA_using_OpenCL
  Squeezenet V1.1 on Cyclone V SoC-FPGA at 450ms/image, 20x faster than ARM A9 processor alone. A project for 2017 Innovate FPGA design con…
  ☆111Updated 7 years ago
• tuna / tapa
  TAPA compiles task-parallel HLS program into high-performance FPGA accelerators.
  ☆174Updated last month
• definelicht / hlslib
  A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
  ☆327Updated 8 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆227Updated last week
• riscv-software-src / riscv-perf-model
  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
  ☆189Updated last week
• sld-columbia / esp
  Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
  ☆384Updated 2 months ago
• debtanu09 / systolic_array_matrix_multiplier
  This is a verilog implementation of 4x4 systolic array multiplier
  ☆59Updated 4 years ago
• esl-epfl / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆217Updated this week
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆168Updated 5 years ago
• SingularityKChen / dl_accelerator
  Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions
  ☆200Updated 5 years ago
• agalimberti / NoCRouter
  RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
  ☆129Updated 7 years ago
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆138Updated 3 months ago
• tom01h / zero-riscy
  zero-riscy CPU Core
  ☆17Updated 7 years ago
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆90Updated 6 years ago
• danshanley / FPU
  IEEE 754 floating point unit in Verilog
  ☆145Updated 9 years ago
• riscv-stc / riscv-matrix-project
  Top project for RISC-V Matrix extension proposal and related opensource implementations.
  ☆34Updated last year
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆68Updated last year
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆105Updated 4 months ago